18.14 FCVTNS (scalar)

Floating-point Convert to Signed integer, rounding to nearest with ties to even (scalar).

Syntax

FCVTNS Wd, Hn ; Half-precision to 32-bit

FCVTNS Xd, Hn ; Half-precision to 64-bit

FCVTNS Wd, Sn ; Single-precision to 32-bit

FCVTNS Xd, Sn ; Single-precision to 64-bit

FCVTNS Wd, Dn ; Double-precision to 32-bit

FCVTNS Xd, Dn ; Double-precision to 64-bit

Where:

Wd
Is the 32-bit name of the general-purpose destination register.
Hn
Is the 16-bit name of the SIMD and FP source register.
Xd
Is the 64-bit name of the general-purpose destination register.
Sn
Is the 32-bit name of the SIMD and FP source register.
Dn
Is the 64-bit name of the SIMD and FP source register.

Operation

Floating-point Convert to Signed integer, rounding to nearest with ties to even (scalar). This instruction converts the floating-point value in the SIMD and FP source register to a 32-bit or 64-bit signed integer using the Round to Nearest rounding mode, and writes the result to the general-purpose destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Rd = signed_convertToIntegerExactTiesToEven(Vn), where R is either W or X.

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