| Non-Confidential |  PDF version | DUI0801J | ||
| ||||
| Home > Advanced SIMD Instructions (32-bit) > VCGT (register) | ||||
| Non-Confidential | PDF version | DUI0801J | ||
| ||||
| Home > Advanced SIMD Instructions (32-bit) > VCGT (register) | ||||
Vector Compare Greater Than.
VCGT{conddatatypeQdQnQm
VCGT{conddatatypeDdDnDm
where:
condis an optional condition code.
datatypemust be one of S8, S16, S32, U8, U16, U32,
or F32.
The result datatype is:
I32 for operand datatypes S32, U32, or
F32.
I16 for operand datatypes S16 or U16.
I8 for operand datatypes S8 or U8.
Qd, Qn, Qmspecifies the destination register, the first operand register, and the second operand register, for a quadword operation.
Dd, Dn, Dmspecifies the destination register, the first operand register, and the second operand register, for a doubleword operation.
VCGT takes the value of each element in a vector, and compares it with the
value of the corresponding element of a second vector. If the condition is true, the
corresponding element in the destination vector is set to all ones. Otherwise, it is set to
all zeros.
| Non-Confidential | PDF version | DUI0801J |
| Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved. |
| Home > Advanced SIMD Instructions (32-bit) > VCGT (register) |