Non-Confidential | PDF version | DUI0801J | ||
| ||||
Home > A64 SIMD Vector Instructions > SQDMLSL, SQDMLSL2 (vector) |
Signed saturating Doubling Multiply-Subtract Long.
SQDMLSL{2}
Vd
.Ta
, Vn
.Tb
, Vm
.Tb
Where:
2
Vd
Ta
4S
or 2D
.
Vn
Tb
Vm
Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD and FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD and FP register. The destination vector elements are twice as long as the elements that are multiplied.
If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.
The SQDMLSL
instruction extracts each source vector from the lower half of each source register, while the SQDMLSL2
instruction extracts each source vector from the upper half of each source register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-60 SQDMLSL{2} (Vector) specifier combinations
<Q> | Ta |
Tb |
---|---|---|
- | 4S | 4H |
2 | 4S | 8H |
- | 2D | 2S |
2 | 2D | 4S |