Arm Compiler armasm User Guide : 20.150 SCVTF (vector, integer)

20.150 SCVTF (vector, integer)

Signed integer Convert to Floating-point (vector).

Syntax

SCVTF Vd.T, Vn.T ; Vector half precision

SCVTF Vd.T, Vn.T ; Vector single-precision and double-precision

Where:

Vd

Is the name of the SIMD and FP destination register

T

Is an arrangement specifier:

Vector half precision: Can be one of 4H or 8H.
Vector single-precision and double-precision: Can be one of 2S, 4S or 2D.

Vn

Is the name of the SIMD and FP source register

Architectures supported (vector)

Supported in the Arm^®v8.2 architecture and later.

Usage

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD and FP destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm^® Architecture Reference Manual Arm^®v8, for Arm^®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.

Related references

20.1 A64 SIMD Vector instructions in alphabetical order

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