19.63 SQADD (scalar)

Signed saturating Add.


SQADD Vd, Vn, Vm


Is a width specifier, and can be one of B, H, S or D.
Is the number of the SIMD and FP destination register.
Is the number of the first SIMD and FP source register.
Is the number of the second SIMD and FP source register.


Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD and FP registers, places the results into a vector, and writes the vector to the destination SIMD and FP register.

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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