13.152 SVC

SuperVisor Call.

Syntax

SVC{cond} #imm

where:

cond

is an optional condition code.

imm

is an expression evaluating to an integer in the range:

  • 0 to 224-1 (a 24-bit value) in an A32 instruction.

  • 0-255 (an 8-bit value) in a T32 instruction.

Operation

The SVC instruction causes an exception. This means that the processor mode changes to Supervisor, the CPSR is saved to the Supervisor mode SPSR, and execution branches to the SVC vector.

imm is ignored by the processor. However, it can be retrieved by the exception handler to determine what service is being requested.

Note:

SVC was called SWI in earlier versions of the A32 assembly language. SWI instructions disassemble to SVC, with a comment to say that this was formerly SWI.

Condition flags

This instruction does not change the flags.

Availability

This instruction is available in A32 and 16-bit T32 and in the Arm®v7 architectures.

There is no 32-bit version of this instruction in T32.

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