13.51 LDR (PC-relative)

Load register. The address is an offset from the PC.

Syntax

LDR{type}{cond}{.W} Rt, label

LDRD{cond} Rt, Rt2, label ; Doubleword

where:

type

can be any one of:

B
unsigned Byte (Zero extend to 32 bits on loads.)
SB
signed Byte (LDR only. Sign extend to 32 bits.)
H
unsigned Halfword (Zero extend to 32 bits on loads.)
SH
signed Halfword (LDR only. Sign extend to 32 bits.)
-
omitted, for Word.
cond
is an optional condition code.
.W
is an optional instruction width specifier.
Rt
is the register to load or store.
Rt2
is the second register to load or store.
label

is a PC-relative expression.

label must be within a limited distance of the current instruction.

Note:

Equivalent syntaxes are available for the STR instruction in A32 code but they are deprecated.

Offset range and architectures

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

The following table shows the possible offsets between the label and the current instruction:

Table 13-11 PC-relative offsets

Instruction Offset range
A32 LDR, LDRB, LDRSB, LDRH, LDRSH a ±4095
A32 LDRD ±255
32-bit T32 LDR, LDRB, LDRSB, LDRH, LDRSH a ±4095
32-bit T32 LDRD b ±1020 c
16-bit T32 LDR d 0-1020 c

LDR (PC-relative) in T32

You can use the .W width specifier to force LDR to generate a 32-bit instruction in T32 code. LDR.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit LDR.

For forward references, LDR without .W always generates a 16-bit instruction in T32 code, even if that results in failure for a target that could be reached using a 32-bit T32 LDR instruction.

Doubleword register restrictions

For 32-bit T32 instructions, you must not specify SP or PC for either Rt or Rt2.

For A32 instructions:

  • Rt must be an even-numbered register.
  • Rt must not be LR.
  • Arm strongly recommends that you do not use R12 for Rt.
  • Rt2 must be R(t + 1).

Use of SP

In A32 code, you can use SP for Rt in LDR word instructions. You can use SP for Rt in LDR non-word A32 instructions but this is deprecated.

In T32 code, you can use SP for Rt in LDR word instructions only. All other uses of SP in these instructions are not permitted in T32 code.

a 

For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In Arm®v4, bits[1:0] of the address loaded must be 0b00. In Armv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in T32 state, otherwise execution continues in A32 state.

b 

In Armv7‑M, LDRD (PC-relative) instructions must be on a word-aligned address.

c 

Must be a multiple of 4.

d 

Rt must be in the range R0-R7. There are no byte, halfword, or doubleword 16-bit instructions.

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