Arm Compiler armasm User Guide : 20.63 FMAX (vector)

20.63 FMAX (vector)

Floating-point Maximum (vector).

Syntax

FMAX Vd.T, Vn.T, Vm.T ; Half-precision

FMAX Vd.T, Vn.T, Vm.T ; Single-precision and double-precision

Where:

T

Is an arrangement specifier:

Half-precision: Can be one of 4H or 8H.
Single-precision and double-precision: Can be one of 2S, 4S or 2D.

Vd

Is the name of the SIMD and FP destination register.

Vn

Is the name of the first SIMD and FP source register.

Vm

Is the name of the second SIMD and FP source register.

Architectures supported (vector)

Supported in the Arm^®v8.2 architecture and later.

Usage

Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD and FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD and FP register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm^® Architecture Reference Manual Arm^®v8, for Arm^®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Related references

20.1 A64 SIMD Vector instructions in alphabetical order

Non-Confidential	PDF version	DUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.