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Home > A64 SIMD Vector Instructions > FMAX (vector) |
Floating-point Maximum (vector).
FMAX
Vd
.T
, Vn
.T
, Vm
.T
; Half-precision
FMAX
Vd
.T
, Vn
.T
, Vm
.T
; Single-precision and double-precision
Where:
T
Is an arrangement specifier:
4H
or 8H
.
2S
, 4S
or 2D
.
Vd
Vn
Vm
Supported in the Arm®v8.2 architecture and later.
Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD and FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD and FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.