9.3 Extension register bank mapping for Advanced SIMD in AArch64 state

The extension register bank is a collection of registers that can be accessed as 8-bit, 16-bit, 32-bit, 64-bit, or 128-bit.

Advanced SIMD and floating-point instructions use the same extension register bank, and is distinct from the Arm® core register bank.

The following figure shows the views of the extension register bank, and the overlap between the different size registers.

Figure 9-2 Extension register bank for Advanced SIMD in AArch64 state
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The mapping between the registers is as follows:

  • D<n> maps to the least significant half of V<n>
  • S<n> maps to the least significant half of D<n>
  • H<n> maps to the least significant half of S<n>
  • B<n> maps to the least significant half of H<n>.

For example, you can access the least significant half of the elements of a vector in V7 by referring to D7.

Registers Q0-Q31 map directly to registers V0-V31.

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