17.49 LDSETAH, LDSETALH, LDSETH, LDSETLH

Atomic bit set on halfword in memory.

Syntax

LDSETAH Ws, Wt, [Xn|SP] ; Acquire general registers

LDSETALH Ws, Wt, [Xn|SP] ; Acquire and release general registers

LDSETH Ws, Wt, [Xn|SP] ; No memory ordering general registers

LDSETLH Ws, Wt, [Xn|SP] ; Release general registers

Where:

Ws
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
Wt
Is the 32-bit name of the general-purpose register to be loaded.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Architectures supported

Supported in the Arm®v8.1 architecture and later.

Usage

Atomic bit set on halfword in memory atomically loads a 16-bit halfword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

  • If the destination register is not WZR, LDSETAH and LDSETALH load from memory with acquire semantics.
  • LDSETLH and LDSETALH store to memory with release semantics.
  • LDSETH has no memory ordering requirements.

For more information about memory ordering semantics see Load-Acquire, Store-Release in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

For information about memory accesses see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

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