19.31 FCVTAU (scalar)

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector).

Syntax

FCVTAU Hd, Hn ; Scalar half precision

FCVTAU Vd, Vn ; Scalar single-precision and double-precision

Where:

Hd
Is the 16-bit name of the SIMD and FP destination register.
Hn
Is the 16-bit name of the SIMD and FP source register.
V
Is a width specifier, and can be either S or D.
d
Is the number of the SIMD and FP destination register.
n
Is the number of the SIMD and FP source register.

Architectures supported (scalar)

Supported in the Arm®v8.2 architecture and later.

Usage

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD and FP destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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