13.60 MCRR and MCRR2

Move to Coprocessor from two general-purpose registers. Depending on the coprocessor, you might be able to specify various additional operations.

Note:

MCRR2 is not supported in Arm®v8.

Syntax

MCRR{cond} coproc, #opcode, Rt, Rt2, CRn

MCRR2{cond} coproc, #opcode, Rt, Rt2, CRn

where:

cond

is an optional condition code.

In A32 code, cond is not permitted for MCRR2.

coproc

is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer whose value must be:

  • In the range 0-15 in Armv7 and earlier.
  • 14 or 15 in Armv8.
opcode
is a 4-bit coprocessor-specific opcode.
Rt, Rt2
are general-purpose registers. Rt and Rt2 must not be PC.
CRn
is a coprocessor register.

Usage

The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

Architectures

These 32-bit instructions are available in A32 and T32.

There are no 16-bit versions of these instructions in T32.

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