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Home > A64 Floating-point Instructions > FCCMP |
Floating-point Conditional quiet Compare (scalar).
FCCMP
Hn
, Hm
, #nzcv
, cond
; Half-precision
FCCMP
Sn
, Sm
, #nzcv
, cond
; Single-precision
FCCMP
Dn
, Dm
, #nzcv
, cond
; Double-precision
Where:
Hn
Hm
Sn
Sm
Dn
Dm
nzcv
cond
The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either or both of the operands are NaNs, they are unordered, and all three of (Operand1 < Operand2), (Operand1 == Operand2) and (Operand1 > Operand2) are false. This case results in the FPSCR flags being set to N=0, Z=0, C=1, and V=1.
Floating-point Conditional quiet Compare (scalar). This instruction compares the two SIMD and FP source register values and writes the result to the PSTATE.{N, Z, C, V} flags. If the condition does not pass then the PSTATE.{N, Z, C, V} flags are set to the flag bit specifier.
It raises an Invalid Operation exception only if either operand is a signaling NaN.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
flags = if
.cond
then compareQuiet(V
n,V
m) else #nzcv