Architectures supported

Supported in the Arm^®v8.1 architecture and later.

Usage

Compare and Swap byte in memory reads an 8-bit byte from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write.

• CASAB and CASALB load from memory with acquire semantics.
• CASLB and CASALB store to memory with release semantics.
• CASB has no memory ordering requirements.

For more information about memory ordering semantics see Load-Acquire, Store-Release in the Arm^® Architecture Reference Manual Arm^®v8, for Arm^®v8‑A architecture profile.

For information about memory accesses see Load/Store addressing modes in the Arm^® Architecture Reference Manual Arm^®v8, for Arm^®v8‑A architecture profile.

The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails.

If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is Ws, is restored to the values held in the register before the instruction was executed.