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Home > Advanced SIMD Instructions (32-bit) > VRSHL (by signed variable) |

Vector Rounding Shift Left by signed variable.

`VRSHL`

{

}.`cond`

{`datatype`

}, `Qd`

,
`Qm`

`Qn`

`VRSHL`

{

}.`cond`

{`datatype`

}, `Dd`

,
`Dm`

`Dn`

where:

`cond`

is an optional condition code.

`datatype`

must be one of

`S8`

,`S16`

,`S32`

,`S64`

,`U8`

,`U16`

,`U32`

, or`U64`

.`Qd`

,`Qm`

,`Qn`

are the destination vector, the first operand vector, and the second operand vector, for a quadword operation.

`Dd`

,`Dm`

,`Dn`

are the destination vector, the first operand vector, and the second operand vector, for a doubleword operation.

`VRSHL`

takes each element in a vector, shifts them by a value from the
least significant byte of the corresponding element of a second vector, and places the
results in the destination vector. If the shift value is positive, the operation is a left
shift. Otherwise, it is a rounding right shift.