ARM® Compiler armasm Reference Guide

Version 6.01


List of Topics

Conventions and Feedback
armasm Command-line Options
armasm command-line syntax
armasm command-line options
--16
--32
--apcs
--arm
--arm_only
--bi
--bigend
--brief_diagnostics
--checkreglist
--cpu
--debug
--depend
--depend_format
--diag_error
--diag_remark
--diag_style
--diag_suppress
--diag_warning
--dllexport_all
--dwarf2
--dwarf3
--errors
--execstack
--exceptions
--exceptions_unwind
--fpmode
--fpu
-g
--help
-i
--keep
--length
--li
--library_type
--list
--littleend
-m
--maxcache
--md
--no_code_gen
--no_esc
--no_execstack
--no_exceptions
--no_exceptions_unwind
--no_hide_all
--no_reduce_paths
--no_regs
--no_terse
--no_unaligned_access
--no_warn
-o
--pd
--predefine
--reduce_paths
--regnames
--report-if-not-wysiwyg
--show_cmdline
--thumb
--tool_variant
--unaligned_access
--unsafe
--untyped_local_labels
--version_number
--via
--vsn
--width
--xref
A32 and T32 Instructions
A32 and T32 instruction summary
Instruction width specifiers
Memory access instructions
General data processing instructions
Flexible second operand (Operand2)
Operand2 as a constant
Operand2 as a register with optional shift
Shift operations
Multiply instructions
Saturating instructions
Parallel instructions
Packing and unpacking instructions
Branch and control instructions
Coprocessor instructions
Miscellaneous instructions
Pseudo-instructions
Condition codes
ADD, SUB, RSB, ADC, SBC, and RSC
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND, ORR, EOR, BIC, and ORN
ASR, LSL, LSR, ROR, and RRX
B, BL, BX, and BLX
BFC and BFI
BKPT
CBZ and CBNZ
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DCPS1 (T32 instruction)
DCPS2 (T32 instruction)
DCPS3 (T32 instruction)
DMB, DSB, and ISB
ERET
HLT
HVC
IT
LDC and STC
LDM and STM
LDR and STR (immediate offset)
LDR and STR (register offset)
LDR and STR, unprivileged
LDR (PC-relative)
LDR (register-relative)
LDR pseudo-instruction
LDA and STL
LDAEX and STLEX
LDREX and STREX
MCR and MCRR
MOV and MVN
MOVT
MOV32 pseudo-instruction
MRC and MRRC
MRS (system coprocessor register to ARM register)
MRS (PSR to general-purpose register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL, MLA, and MLS
NEG pseudo-instruction
NOP
Parallel add and subtract
PKHBT and PKHTB
PLD, PLDW, and PLI
PUSH and POP
QADD, QSUB, QDADD, and QDSUB
REV, REV16, REVSH, and RBIT
RFE
SBFX and UBFX
SDIV and UDIV
SEL
SETEND
SEV, SEVL, WFE, WFI, and YIELD
SMC
SMLAD and SMLSD
SMLALxy
SMLALD and SMLSLD
SMMUL, SMMLA, and SMMLS
SMUAD{X} and SMUSD{X}
SMULWy and SMLAWy
SMULxy and SMLAxy
SRS
SSAT and USAT
SSAT16 and USAT16
SUBS pc, lr
SVC
SXT, SXTA, UXT, and UXTA
SYS
TBB and TBH
TST and TEQ
UMAAL
UMULL, UMLAL, SMULL, and SMLAL
UND pseudo-instruction
USAD8 and USADA8
Advanced SIMD and Floating-point Programming (32-bit)
Advanced SIMD and floating-point instruction summary
Shared Advanced SIMD and floating-point instructions
Advanced SIMD logical and compare operations
Advanced SIMD general data processing instructions
Advanced SIMD shift instructions
Advanced SIMD general arithmetic instructions
Advanced SIMD multiply instructions
Advanced SIMD load and store element and structure instructions
Interleaving provided by load and store, element and structure instructions
Alignment restrictions in load and store, element and structure instructions
Advanced SIMD and floating-point pseudo-instructions
Floating-point instructions
Cryptographic instructions
V{Q}{R}SHL (by signed variable)
V{Q}ABS and V{Q}NEG
V{Q}ADD, VADDL, VADDW, V{Q}SUB, VSUBL, and VSUBW
V{R}ADDHN and V{R}SUBHN
V{R}HADD and VHSUB
V{R}SHR (by immediate)
V{R}SHRN (by immediate)
V{R}SRA (by immediate)
VABA{L} and VABD{L}
VABS, VNEG, and VSQRT
VACGE and VACGT
VACLE and VACLT
VADD, VSUB, and VDIV
VAND, VBIC, VEOR, VORN, and VORR (register)
VAND and VORN (immediate)
VBIC and VORR (immediate)
VBIF, VBIT, and VBSL
VCEQ, VCGE, VCGT, VCLE, and VCLT
VCLE and VCLT
VCLS, VCLZ, and VCNT
VCMP, VCMPE
VCVT (between fixed-point or integer, and floating-point)
VCVT (from floating-point to integer with directed rounding modes)
VCVT (between half-precision and single-precision floating-point)
VCVT (between single-precision and double-precision)
VCVT (between floating-point and integer)
VCVT (from floating-point to integer with directed rounding modes)
VCVT (between floating-point and fixed-point)
VCVTB, VCVTT (half-precision extension)
VCVTB, VCVTT (between half-precision and double-precision)
VDUP
VEXT
VFMA, VFMS
VFNMA, VFNMS
VLDM, VSTM, VPOP, and VPUSH
VLDR and VSTR
VLDn and VSTn (single n-element structure to one lane)
VLDn (single n-element structure to all lanes)
VLDn and VSTn (multiple n-element structures)
VLDR pseudo-instruction
VLDR and VSTR (post-increment and pre-decrement)
VMAX, VMIN, VPMAX, and VPMIN
VMAXNM, VMINNM (Advanced SIMD)
VMAXNM, VMINNM (floating-point)
VMOV
VMOV, VMVN (immediate)
VMOV, VMVN (register)
VMOV (between two ARM registers and one or two extension registers)
VMOV (between an ARM register and a scalar)
VMOV (between one ARM register and single precision floating-point register)
VMOV2
VMOVL, V{Q}MOVN, VQMOVUN
VMRS and VMSR
VMUL, VMLA, VMLS, VNMUL, VNMLA, and VNMLS
VMUL{L}, VMLA{L}, and VMLS{L}
VMUL{L}, VMLA{L}, and VMLS{L} (by scalar)
VPADD{L}, VPADAL
VQ{R}DMULH (by vector or by scalar)
VQ{R}SHR{U}N (by immediate)
VQDMULL, VQDMLAL, and VQDMLSL (by vector or by scalar)
VRECPE and VRSQRTE
VRECPS and VRSQRTS
VREV
VRINT (Advanced SIMD)
VRINT (floating-point)
VSEL
VSHL, VQSHL, VQSHLU, and VSHLL (by immediate)
VSLI and VSRI
VSWP
VTBL, VTBX
VTRN
VTST
VUZP, VZIP
A64 General Instructions
A64 general instructions in alphabetical order
Register restrictions for A64 instructions
ADC
ADCS
ADD (extended register)
ADD (immediate)
ADD (shifted register)
ADDS (extended register)
ADDS (immediate)
ADDS (shifted register)
ADR
ADRL pseudo-instruction
ADRP
AND (immediate)
AND (shifted register)
ANDS (immediate)
ANDS (shifted register)
ASR (register)
ASR (immediate)
ASRV
AT
B.cond
B
BFI
BFM
BFXIL
BIC (shifted register)
BICS (shifted register)
BL
BLR
BR
BRK
CBNZ
CBZ
CCMN (immediate)
CCMN (register)
CCMP (immediate)
CCMP (register)
CINC
CINV
CLREX
CLS
CLZ
CMN (extended register)
CMN (immediate)
CMN (shifted register)
CMP (extended register)
CMP (immediate)
CMP (shifted register)
CNEG
CRC32B, CRC32H, CRC32W, CRC32X
CRC32CB, CRC32CH, CRC32CW, CRC32CX
CSEL
CSET
CSETM
CSINC
CSINV
CSNEG
DC
DCPS1 (A64 instruction)
DCPS2 (A64 instruction)
DCPS3 (A64 instruction)
DMB
DRPS
DSB
EON (shifted register)
EOR (immediate)
EOR (shifted register)
ERET
EXTR
HINT
HLT
HVC
IC
ISB
LSL (register)
LSL (immediate)
LSLV
LSR (register)
LSR (immediate)
LSRV
MADD
MNEG
MOV (to or from SP)
MOV (inverted wide immediate)
MOV (wide immediate)
MOV (bitmask immediate)
MOV (register)
MOVK
MOVL pseudo-instruction
MOVN
MOVZ
MRS
MSR (immediate)
MSR (register)
MSUB
MUL
MVN
NEG (shifted register)
NEGS
NGC
NGCS
NOP
ORN (shifted register)
ORR (immediate)
ORR (shifted register)
RBIT
RET
REV
REV16
REV32
ROR (immediate)
ROR (register)
RORV
SBC
SBCS
SBFIZ
SBFM
SBFX
SDIV
SEV
SEVL
SMADDL
SMC
SMNEGL
SMSUBL
SMULH
SMULL
SUB (extended register)
SUB (immediate)
SUB (shifted register)
SUBS (extended register)
SUBS (immediate)
SUBS (shifted register)
SVC
SXTB
SXTH
SXTW
SYS
SYSL
TBNZ
TBZ
TLBI
TST (immediate)
TST (shifted register)
UBFIZ
UBFM
UBFX
UDIV
UMADDL
UMNEGL
UMSUBL
UMULH
UMULL
UXTB
UXTH
WFE
WFI
YIELD
A64 Data Transfer Instructions
A64 data transfer instructions in alphabetical order
Register restrictions for A64 instructions
LDAR
LDARB
LDARH
LDAXP
LDAXR
LDAXRB
LDAXRH
LDNP (SIMD and FP)
LDNP
LDP (SIMD and FP)
LDP
LDPSW
LDR (immediate, SIMD and FP)
LDR (immediate)
LDR (literal, SIMD and FP)
LDR (literal)
LDR pseudo-instruction
LDR (register, SIMD and FP)
LDR (register)
LDRB (immediate)
LDRB (register)
LDRH (immediate)
LDRH (register)
LDRSB (immediate)
LDRSB (register)
LDRSH (immediate)
LDRSH (register)
LDRSW (immediate)
LDRSW (literal)
LDRSW (register)
LDTR
LDTRB
LDTRH
LDTRSB
LDTRSH
LDTRSW
LDUR (SIMD and FP)
LDUR
LDURB
LDURH
LDURSB
LDURSH
LDURSW
LDXP
LDXR
LDXRB
LDXRH
PRFM (immediate)
PRFM (literal)
PRFM (register)
PRFUM
STLR
STLRB
STLRH
STLXP
STLXR
STLXRB
STLXRH
STNP (SIMD and FP)
STNP
STP (SIMD and FP)
STP
STR (immediate, SIMD and FP)
STR (immediate)
STR (register, SIMD and FP)
STR (register)
STRB (immediate)
STRB (register)
STRH (immediate)
STRH (register)
STTR
STTRB
STTRH
STUR (SIMD and FP)
STUR
STURB
STURH
STXP
STXR
STXRB
STXRH
A64 Floating-point Instructions
A64 floating-point instructions in alphabetical order
FABS (scalar)
FADD (scalar)
FCCMP
FCCMPE
FCMP
FCMPE
FCSEL
FCVT
FCVTAS (scalar)
FCVTAU (scalar)
FCVTMS (scalar)
FCVTMU (scalar)
FCVTNS (scalar)
FCVTNU (scalar)
FCVTPS (scalar)
FCVTPU (scalar)
FCVTZS (scalar, fixed-point)
FCVTZS (scalar, integer)
FCVTZU (scalar, fixed-point)
FCVTZU (scalar, integer)
FDIV (scalar)
FMADD
FMAX (scalar)
FMAXNM (scalar)
FMIN (scalar)
FMINNM (scalar)
FMOV (register)
FMOV (general)
FMOV (scalar, immediate)
FMSUB
FMUL (scalar)
FNEG (scalar)
FNMADD
FNMSUB
FNMUL
FRINTA (scalar)
FRINTI (scalar)
FRINTM (scalar)
FRINTN (scalar)
FRINTP (scalar)
FRINTX (scalar)
FRINTZ (scalar)
FSQRT (scalar)
FSUB (scalar)
SCVTF (scalar, fixed-point)
SCVTF (scalar, integer)
UCVTF (scalar, fixed-point)
UCVTF (scalar, integer)
A64 SIMD Scalar Instructions
A64 SIMD scalar instructions in alphabetical order
ABS (scalar)
ADD (scalar)
ADDP (scalar)
CMEQ (scalar, register)
CMEQ (scalar, zero)
CMGE (scalar, register)
CMGE (scalar, zero)
CMGT (scalar, register)
CMGT (scalar, zero)
CMHI (scalar, register)
CMHS (scalar, register)
CMLE (scalar, zero)
CMLT (scalar, zero)
CMTST (scalar)
DUP (scalar, element)
FABD (scalar)
FACGE (scalar)
FACGT (scalar)
FADDP (scalar)
FCMEQ (scalar, register)
FCMEQ (scalar, zero)
FCMGE (scalar, register)
FCMGE (scalar, zero)
FCMGT (scalar, register)
FCMGT (scalar, zero)
FCMLE (scalar, zero)
FCMLT (scalar, zero)
FCVTAS (scalar)
FCVTAU (scalar)
FCVTMS (scalar)
FCVTMU (scalar)
FCVTNS (scalar)
FCVTNU (scalar)
FCVTPS (scalar)
FCVTPU (scalar)
FCVTXN (scalar)
FCVTZS (scalar, fixed-point)
FCVTZS (scalar, integer)
FCVTZU (scalar, fixed-point)
FCVTZU (scalar, integer)
FMAXNMP (scalar)
FMAXP (scalar)
FMINNMP (scalar)
FMINP (scalar)
FMLA (scalar, by element)
FMLS (scalar, by element)
FMUL (scalar, by element)
FMULX (scalar, by element)
FMULX (scalar)
FRECPE (scalar)
FRECPS (scalar)
FRECPX (scalar)
FRSQRTE (scalar)
FRSQRTS (scalar)
MOV (scalar)
NEG (scalar)
SCVTF (scalar, fixed-point)
SCVTF (scalar, integer)
SHL (scalar)
SLI (scalar)
SQABS (scalar)
SQADD (scalar)
SQDMLAL (scalar, by element)
SQDMLAL (scalar)
SQDMLSL (scalar, by element)
SQDMLSL (scalar)
SQDMULH (scalar, by element)
SQDMULH (scalar)
SQDMULL (scalar, by element)
SQDMULL (scalar)
SQNEG (scalar)
SQRDMULH (scalar, by element)
SQRDMULH (scalar)
SQRSHL (scalar)
SQRSHRN (scalar)
SQRSHRUN (scalar)
SQSHL (scalar, immediate)
SQSHL (scalar, register)
SQSHLU (scalar)
SQSHRN (scalar)
SQSHRUN (scalar)
SQSUB (scalar)
SQXTN (scalar)
SQXTUN (scalar)
SRI (scalar)
SRSHL (scalar)
SRSHR (scalar)
SRSRA (scalar)
SSHL (scalar)
SSHR (scalar)
SSRA (scalar)
SUB (scalar)
SUQADD (scalar)
UCVTF (scalar, fixed-point)
UCVTF (scalar, integer)
UQADD (scalar)
UQRSHL (scalar)
UQRSHRN (scalar)
UQSHL (scalar, immediate)
UQSHL (scalar, register)
UQSHRN (scalar)
UQSUB (scalar)
UQXTN (scalar)
URSHL (scalar)
URSHR (scalar)
URSRA (scalar)
USHL (scalar)
USHR (scalar)
USQADD (scalar)
USRA (scalar)
A64 SIMD Vector Instructions
A64 SIMD vector instructions in alphabetical order
ABS (vector)
ADD (vector)
ADDHN, ADDHN2 (vector)
ADDP (vector)
ADDV (vector)
AND (vector)
BIC (vector, immediate)
BIC (vector, register)
BIF (vector)
BIT (vector)
BSL (vector)
CLS (vector)
CLZ (vector)
CMEQ (vector, register)
CMEQ (vector, zero)
CMGE (vector, register)
CMGE (vector, zero)
CMGT (vector, register)
CMGT (vector, zero)
CMHI (vector, register)
CMHS (vector, register)
CMLE (vector, zero)
CMLT (vector, zero)
CMTST (vector)
CNT (vector)
DUP (vector, element)
DUP (vector, general)
EOR (vector)
EXT (vector)
FABD (vector)
FABS (vector)
FACGE (vector)
FACGT (vector)
FADD (vector)
FADDP (vector)
FCMEQ (vector, register)
FCMEQ (vector, zero)
FCMGE (vector, register)
FCMGE (vector, zero)
FCMGT (vector, register)
FCMGT (vector, zero)
FCMLE (vector, zero)
FCMLT (vector, zero)
FCVTAS (vector)
FCVTAU (vector)
FCVTL, FCVTL2 (vector)
FCVTMS (vector)
FCVTMU (vector)
FCVTN, FCVTN2 (vector)
FCVTNS (vector)
FCVTNU (vector)
FCVTPS (vector)
FCVTPU (vector)
FCVTXN, FCVTXN2 (vector)
FCVTZS (vector, fixed-point)
FCVTZS (vector, integer)
FCVTZU (vector, fixed-point)
FCVTZU (vector, integer)
FDIV (vector)
FMAX (vector)
FMAXNM (vector)
FMAXNMP (vector)
FMAXNMV (vector)
FMAXP (vector)
FMAXV (vector)
FMIN (vector)
FMINNM (vector)
FMINNMP (vector)
FMINNMV (vector)
FMINP (vector)
FMINV (vector)
FMLA (vector, by element)
FMLA (vector)
FMLS (vector, by element)
FMLS (vector)
FMOV (vector, immediate)
FMUL (vector, by element)
FMUL (vector)
FMULX (vector, by element)
FMULX (vector)
FNEG (vector)
FRECPE (vector)
FRECPS (vector)
FRINTA (vector)
FRINTI (vector)
FRINTM (vector)
FRINTN (vector)
FRINTP (vector)
FRINTX (vector)
FRINTZ (vector)
FRSQRTE (vector)
FRSQRTS (vector)
FSQRT (vector)
FSUB (vector)
INS (vector, element)
INS (vector, general)
LD1 (vector, multiple structures)
LD1 (vector, single structure)
LD1R (vector)
LD2 (vector, multiple structures)
LD2 (vector, single structure)
LD2R (vector)
LD3 (vector, multiple structures)
LD3 (vector, single structure)
LD3R (vector)
LD4 (vector, multiple structures)
LD4 (vector, single structure)
LD4R (vector)
MLA (vector, by element)
MLA (vector)
MLS (vector, by element)
MLS (vector)
MOV (vector, element)
MOV (vector, from general)
MOV (vector)
MOV (vector, to general)
MOVI (vector)
MUL (vector, by element)
MUL (vector)
MVN (vector)
MVNI (vector)
NEG (vector)
NOT (vector)
ORN (vector)
ORR (vector, immediate)
ORR (vector, register)
PMUL (vector)
PMULL, PMULL2 (vector)
RADDHN, RADDHN2 (vector)
RBIT (vector)
REV16 (vector)
REV32 (vector)
REV64 (vector)
RSHRN, RSHRN2 (vector)
RSUBHN, RSUBHN2 (vector)
SABA (vector)
SABAL, SABAL2 (vector)
SABD (vector)
SABDL, SABDL2 (vector)
SADALP (vector)
SADDL, SADDL2 (vector)
SADDLP (vector)
SADDLV (vector)
SADDW, SADDW2 (vector)
SCVTF (vector, fixed-point)
SCVTF (vector, integer)
SHADD (vector)
SHL (vector)
SHLL, SHLL2 (vector)
SHRN, SHRN2 (vector)
SHSUB (vector)
SLI (vector)
SMAX (vector)
SMAXP (vector)
SMAXV (vector)
SMIN (vector)
SMINP (vector)
SMINV (vector)
SMLAL, SMLAL2 (vector, by element)
SMLAL, SMLAL2 (vector)
SMLSL, SMLSL2 (vector, by element)
SMLSL, SMLSL2 (vector)
SMOV (vector)
SMULL, SMULL2 (vector, by element)
SMULL, SMULL2 (vector)
SQABS (vector)
SQADD (vector)
SQDMLAL, SQDMLAL2 (vector, by element)
SQDMLAL, SQDMLAL2 (vector)
SQDMLSL, SQDMLSL2 (vector, by element)
SQDMLSL, SQDMLSL2 (vector)
SQDMULH (vector, by element)
SQDMULH (vector)
SQDMULL, SQDMULL2 (vector, by element)
SQDMULL, SQDMULL2 (vector)
SQNEG (vector)
SQRDMULH (vector, by element)
SQRDMULH (vector)
SQRSHL (vector)
SQRSHRN, SQRSHRN2 (vector)
SQRSHRUN, SQRSHRUN2 (vector)
SQSHL (vector, immediate)
SQSHL (vector, register)
SQSHLU (vector)
SQSHRN, SQSHRN2 (vector)
SQSHRUN, SQSHRUN2 (vector)
SQSUB (vector)
SQXTN, SQXTN2 (vector)
SQXTUN, SQXTUN2 (vector)
SRHADD (vector)
SRI (vector)
SRSHL (vector)
SRSHR (vector)
SRSRA (vector)
SSHL (vector)
SSHLL, SSHLL2 (vector)
SSHR (vector)
SSRA (vector)
SSUBL, SSUBL2 (vector)
SSUBW, SSUBW2 (vector)
ST1 (vector, multiple structures)
ST1 (vector, single structure)
ST2 (vector, multiple structures)
ST2 (vector, single structure)
ST3 (vector, multiple structures)
ST3 (vector, single structure)
ST4 (vector, multiple structures)
ST4 (vector, single structure)
SUB (vector)
SUBHN, SUBHN2 (vector)
SUQADD (vector)
SXTL, SXTL2 (vector)
TBL (vector)
TBX (vector)
TRN1 (vector)
TRN2 (vector)
UABA (vector)
UABAL, UABAL2 (vector)
UABD (vector)
UABDL, UABDL2 (vector)
UADALP (vector)
UADDL, UADDL2 (vector)
UADDLP (vector)
UADDLV (vector)
UADDW, UADDW2 (vector)
UCVTF (vector, fixed-point)
UCVTF (vector, integer)
UHADD (vector)
UHSUB (vector)
UMAX (vector)
UMAXP (vector)
UMAXV (vector)
UMIN (vector)
UMINP (vector)
UMINV (vector)
UMLAL, UMLAL2 (vector, by element)
UMLAL, UMLAL2 (vector)
UMLSL, UMLSL2 (vector, by element)
UMLSL, UMLSL2 (vector)
UMOV (vector)
UMULL, UMULL2 (vector, by element)
UMULL, UMULL2 (vector)
UQADD (vector)
UQRSHL (vector)
UQRSHRN, UQRSHRN2 (vector)
UQSHL (vector, immediate)
UQSHL (vector, register)
UQSHRN, UQSHRN2 (vector)
UQSUB (vector)
UQXTN, UQXTN2 (vector)
URECPE (vector)
URHADD (vector)
URSHL (vector)
URSHR (vector)
URSQRTE (vector)
URSRA (vector)
USHL (vector)
USHLL, USHLL2 (vector)
USHR (vector)
USQADD (vector)
USRA (vector)
USUBL, USUBL2 (vector)
USUBW, USUBW2 (vector)
UXTL, UXTL2 (vector)
UZP1 (vector)
UZP2 (vector)
XTN, XTN2 (vector)
ZIP1 (vector)
ZIP2 (vector)
Directives Reference
Alphabetical list of directives
Symbol definition directives
Data definition directives
About assembly control directives
About frame directives
Reporting directives
Instruction set and syntax selection directives
Miscellaneous directives
ALIAS
ALIGN
AREA
ARM, THUMB, CODE16 and CODE32
ASSERT
ATTR
CN
COMMON
CP
DATA
DCB
DCD and DCDU
DCDO
DCFD and DCFDU
DCFS and DCFSU
DCI
DCO and DCOU
DCQ and DCQU
DCW and DCWU
END
ENDFUNC or ENDP
ENTRY
EQU
EXPORT or GLOBAL
EXPORTAS
FIELD
FRAME ADDRESS
FRAME POP
FRAME PUSH
FRAME REGISTER
FRAME RESTORE
FRAME RETURN ADDRESS
FRAME SAVE
FRAME STATE REMEMBER
FRAME STATE RESTORE
FRAME UNWIND ON
FRAME UNWIND OFF
FUNCTION or PROC
GBLA, GBLL, and GBLS
GET or INCLUDE
IMPORT and EXTERN
INCBIN
IF, ELSE, ENDIF, and ELIF
INFO
KEEP
LCLA, LCLL, and LCLS
LTORG
MACRO and MEND
MAP
MEXIT
NOFP
OPT
QN, DN, and SN
RELOC
REQUIRE
REQUIRE8 and PRESERVE8
RLIST
RN
ROUT
SETA, SETL, and SETS
SPACE or FILL
TTL and SUBT
WHILE and WEND
WN and XN
Via File Syntax
Overview of via files
Via file syntax

List of Tables

1. Supported ARM processors and architectures
2. Severity of diagnostic messages
3. Specifying a command-line option and an AREA directive for GNU-stack sections
4. Summary of instructions
5. Condition code suffixes
6. PC-relative offsets
7. register-relative offsets
8. Branch instruction availability and range
9. Permitted instructions inside an IT block
10. Offsets and availability, LDR/STR, word, halfword, and byte
11. Options and availability, LDR/STR (register offsets)
12. Offsets and availability, LDR/STR (User mode)
13. PC-relative offsets
14. Register-relative offsets
15. Range and encoding of expr
16. Summary of Advanced SIMD instructions
17. Summary of shared Advanced SIMD and floating-point instructions
18. Summary of floating-point instructions
19. Patterns for immediate value
20. Permitted combinations of parameters
21. Permitted combinations of parameters
22. Permitted combinations of parameters
23. Available immediate values
24.
25. Results for out-of-range inputs
26. Results for out-of-range inputs
27. Operation of doubleword VZIP.8
28. Operation of quadword VZIP.32
29. Operation of doubleword VUZP.8
30. Operation of quadword VUZP.32
31. Location of general instructions
32. ADD (64-bit general registers) specifier combinations
33. ADDS (64-bit general registers) specifier combinations
34. CMN (64-bit general registers) specifier combinations
35. CMP (64-bit general registers) specifier combinations
36. Data memory barrier options
37. Data synchronization barrier options
38. SUB (64-bit general registers) specifier combinations
39. SUBS (64-bit general registers) specifier combinations
40. Location of data transfer instructions
41. LDR (register, SIMD and FP) specifier combinations
42. LDR (register) specifier combinations
43. LDRB (register) specifier combinations
44. LDRH (register) specifier combinations
45. LDRSB (register) specifier combinations
46. LDRSH (register) specifier combinations
47. LDRSW (register) specifier combinations
48. PRFM (immediate) type options
49. PRFM (immediate) target options
50. PRFM (immediate) policy options
51. PRFM (literal) type options
52. PRFM (literal) target options
53. PRFM (literal) policy options
54. PRFM (register) type options
55. PRFM (register) target options
56. PRFM (register) policy options
57. PRFM (register) specifier combinations
58. PRFUM type options
59. PRFUM target options
60. PRFUM policy options
61. STR (register, SIMD and FP) specifier combinations
62. STR (register) specifier combinations
63. STRB (register) specifier combinations
64. STRH (register) specifier combinations
65. Location of floating-point instructions
66. Location of SIMD scalar instructions
67. DUP (Scalar) specifier combinations
68. FADDP specifier combinations
69. FCVTZS (Scalar) specifier combinations
70. FCVTZU (Scalar) specifier combinations
71. FMAXNMP specifier combinations
72. FMAXP specifier combinations
73. FMINNMP specifier combinations
74. FMINP specifier combinations
75. FMLA (Scalar) specifier combinations
76. FMLS (Scalar) specifier combinations
77. FMUL (Scalar) specifier combinations
78. FMULX (Scalar) specifier combinations
79. MOV specifier combinations
80. SCVTF (Scalar) specifier combinations
81. SQDMLAL (Scalar) specifier combinations
82. SQDMLAL (Scalar) specifier combinations
83. SQDMLSL (Scalar) specifier combinations
84. SQDMLSL (Scalar) specifier combinations
85. SQDMULH (Scalar) specifier combinations
86. SQDMULL (Scalar) specifier combinations
87. SQDMULL (Scalar) specifier combinations
88. SQRDMULH (Scalar) specifier combinations
89. SQRSHRN (Scalar) specifier combinations
90. SQRSHRUN (Scalar) specifier combinations
91. SQSHL (Scalar) specifier combinations
92. SQSHLU (Scalar) specifier combinations
93. SQSHRN (Scalar) specifier combinations
94. SQSHRUN (Scalar) specifier combinations
95. SQXTN (Scalar) specifier combinations
96. SQXTUN (Scalar) specifier combinations
97. UCVTF (Scalar) specifier combinations
98. UQRSHRN (Scalar) specifier combinations
99. UQSHL (Scalar) specifier combinations
100. UQSHRN (Scalar) specifier combinations
101. UQXTN (Scalar) specifier combinations
102. Location of SIMD Vector instructions
103. ADDHN, ADDHN2 specifier combinations
104. ADDV specifier combinations
105. DUP (Vector) specifier combinations
106. DUP specifier combinations
107. EXT specifier combinations
108. FCVTL, FCVTL2 specifier combinations
109. FCVTN, FCVTN2 specifier combinations
110. FCVTXN{2} (Vector) specifier combinations
111. FCVTZS (Vector) specifier combinations
112. FCVTZU (Vector) specifier combinations
113. FMLA (Vector) specifier combinations
114. FMLS (Vector) specifier combinations
115. FMUL (Vector) specifier combinations
116. FMULX (Vector) specifier combinations
117. INS specifier combinations
118. INS specifier combinations
119. LD1 (One register, immediate offset) specifier combinations
120. LD1 (Two registers, immediate offset) specifier combinations
121. LD1 (Three registers, immediate offset) specifier combinations
122. LD1 (Four registers, immediate offset) specifier combinations
123. LD1R (Immediate offset) specifier combinations
124. LD2R (Immediate offset) specifier combinations
125. LD3R (Immediate offset) specifier combinations
126. LD4R (Immediate offset) specifier combinations
127. MLA specifier combinations
128. MLS specifier combinations
129. MOV specifier combinations
130. MOV specifier combinations
131. MUL specifier combinations
132. PMULL, PMULL2 specifier combinations
133. RADDHN, RADDHN2 specifier combinations
134. RSHRN, RSHRN2 specifier combinations
135. RSUBHN, RSUBHN2 specifier combinations
136. SABAL, SABAL2 specifier combinations
137. SABDL, SABDL2 specifier combinations
138. SADALP specifier combinations
139. SADDL, SADDL2 specifier combinations
140. SADDLP specifier combinations
141. SADDLV specifier combinations
142. SADDW, SADDW2 specifier combinations
143. SCVTF (Vector) specifier combinations
144. SHL (Vector) specifier combinations
145. SHLL, SHLL2 specifier combinations
146. SHRN, SHRN2 specifier combinations
147. SLI (Vector) specifier combinations
148. SMAXV specifier combinations
149. SMINV specifier combinations
150. SMLAL, SMLAL2 specifier combinations
151. SMLAL, SMLAL2 specifier combinations
152. SMLSL, SMLSL2 specifier combinations
153. SMLSL, SMLSL2 specifier combinations
154. SMOV (32-bit) specifier combinations
155. SMOV (64-bit) specifier combinations
156. SMULL, SMULL2 specifier combinations
157. SMULL, SMULL2 specifier combinations
158. SQDMLAL{2} (Vector) specifier combinations
159. SQDMLAL{2} (Vector) specifier combinations
160. SQDMLSL{2} (Vector) specifier combinations
161. SQDMLSL{2} (Vector) specifier combinations
162. SQDMULH (Vector) specifier combinations
163. SQDMULL{2} (Vector) specifier combinations
164. SQDMULL{2} (Vector) specifier combinations
165. SQRDMULH (Vector) specifier combinations
166. SQRSHRN{2} (Vector) specifier combinations
167. SQRSHRUN{2} (Vector) specifier combinations
168. SQSHL (Vector) specifier combinations
169. SQSHLU (Vector) specifier combinations
170. SQSHRN{2} (Vector) specifier combinations
171. SQSHRUN{2} (Vector) specifier combinations
172. SQXTN{2} (Vector) specifier combinations
173. SQXTUN{2} (Vector) specifier combinations
174. SRI (Vector) specifier combinations
175. SRSHR (Vector) specifier combinations
176. SRSRA (Vector) specifier combinations
177. SSHLL, SSHLL2 specifier combinations
178. SSHR (Vector) specifier combinations
179. SSRA (Vector) specifier combinations
180. SSUBL, SSUBL2 specifier combinations
181. SSUBW, SSUBW2 specifier combinations
182. ST1 (One register, immediate offset) specifier combinations
183. ST1 (Two registers, immediate offset) specifier combinations
184. ST1 (Three registers, immediate offset) specifier combinations
185. ST1 (Four registers, immediate offset) specifier combinations
186. SUBHN, SUBHN2 specifier combinations
187. SXTL, SXTL2 specifier combinations
188. UABAL, UABAL2 specifier combinations
189. UABDL, UABDL2 specifier combinations
190. UADALP specifier combinations
191. UADDL, UADDL2 specifier combinations
192. UADDLP specifier combinations
193. UADDLV specifier combinations
194. UADDW, UADDW2 specifier combinations
195. UCVTF (Vector) specifier combinations
196. UMAXV specifier combinations
197. UMINV specifier combinations
198. UMLAL, UMLAL2 specifier combinations
199. UMLAL, UMLAL2 specifier combinations
200. UMLSL, UMLSL2 specifier combinations
201. UMLSL, UMLSL2 specifier combinations
202. UMOV (32-bit) specifier combinations
203. UMULL, UMULL2 specifier combinations
204. UMULL, UMULL2 specifier combinations
205. UQRSHRN{2} (Vector) specifier combinations
206. UQSHL (Vector) specifier combinations
207. UQSHRN{2} (Vector) specifier combinations
208. UQXTN{2} (Vector) specifier combinations
209. URSHR (Vector) specifier combinations
210. URSRA (Vector) specifier combinations
211. USHLL, USHLL2 specifier combinations
212. USHR (Vector) specifier combinations
213. USRA (Vector) specifier combinations
214. USUBL, USUBL2 specifier combinations
215. USUBW, USUBW2 specifier combinations
216. UXTL, UXTL2 specifier combinations
217. XTN, XTN2 specifier combinations
218. Location of directives
219. OPT directive settings

Proprietary Notice

Words and logos marked with ™ or ® are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A14 March 2014ARM Compiler v6.00 Release
Revision B15 December 2014ARM Compiler v6.01 Release
Copyright © 2014 ARM. All rights reserved.ARM DUI 0802B
Non-ConfidentialID121814