Fast Models Reference Manual

Version 9.1


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Other information
1 Introduction to the Fast Models Reference Manual
1.1 About the models
2 Accuracy and Functionality in Fast Models
2.1 Model capabilities
2.2 Fast Models accuracy
2.2.1 How accurate are Fast Models?
2.2.2 Timing accuracy of Fast Models
2.2.3 Bus traffic in Fast Models
2.2.4 Instruction prefetch in Fast Models
2.2.5 Out-of-order execution and write-buffers in Fast Models
2.2.6 Caches in Fast Models
2.3 Processor implementation
2.3.1 Caches in PV models
2.3.2 CP14 Debug coprocessor
2.3.3 MicroTLBs
2.3.4 TLBs in PV models
2.3.5 Memory access in PV models
2.3.6 Timing in PV models
2.3.7 VIC port in PV models
2.4 Processor CADI implementation
2.5 CADI interactions with processor behavior
2.6 CADI sync watchpoints
2.7 Non-CADI sync watchpoints
2.7.1 syncLevel definitions
2.7.2 Controlling and observing the syncLevel
2.8 SCADI
2.8.1 About SCADI
2.8.2 Intended uses of CADI and SCADI
2.8.3 Responsibilities of the SCADI caller
2.8.4 SCADI interface access
2.8.5 SCADI semantics
2.9 TelnetTerminal - about
2.10 User mode network set up
2.10.1 User mode networking
2.10.2 Setting-up a network connection for Microsoft Windows
2.10.3 Configuring the networking environment for Microsoft Windows
2.10.4 Usage of tap_setup_32.exe or tap_setup_64.exe for Microsoft Windows
2.10.5 Uninstalling for Microsoft Windows
2.10.6 Setting-up a network connection for Linux
2.10.7 Configuring the networking environment for Linux
2.10.8 Disabling and re-enabling networking for Linux
2.10.9 Uninstalling networking for Linux
3 Protocols in Fast Models
3.1 Protocols in Fast Models - about
3.2 AMBA-PV protocols - about
3.3 Clocking protocols - about
3.4 Debug interface protocols - about
3.5 Processor protocols - about
3.6 Signaling protocols - about
3.7 AMBAPV protocol
3.8 AMBAPVACE protocol
3.9 AMBAPVSignal protocol
3.10 AMBAPVSignalState protocol
3.11 AMBAPVValue protocol
3.12 AMBAPVValue64 protocol
3.13 AMBAPVValueState protocol
3.14 AMBAPVValueState64 protocol
3.15 AudioControl protocol
3.16 CADIDisassemblerProtocol protocol
3.17 CADIProtocol protocol
3.18 CharacterLCD protocol
3.19 ClockRateControl protocol
3.20 CounterInterface protocol
3.21 FlashLoaderPort protocol
3.22 GICv3Comms protocol
3.23 GUIPollCallback protocol
3.24 ICS307Configuration protocol
3.25 InstructionCount protocol
3.26 KeyboardStatus protocol
3.27 LCD protocol
3.28 LCDLayoutInfo protocol
3.29 MMC_Protocol protocol
3.30 MouseStatus protocol
3.31 PL080_DMAC_DmaPortProtocol protocol
3.32 PS2Data protocol
3.33 PVBusSlaveControl protocol
3.34 PVDevice protocol
3.35 PVTransactionMaster protocol
3.36 SerialData protocol
3.37 Signal protocol
3.38 StateSignal protocol
3.39 TimerControl protocol
3.40 TimerControl64 protocol
3.41 TimerCallback protocol
3.42 TimerCallback64 protocol
3.43 TZFilterControl protocol
3.44 v8EmbeddedCrossTrigger_controlprotocol protocol
3.45 Value protocol
3.46 Value_64 protocol
3.47 ValueState protocol
3.48 VirtualEthernet protocol
4 Processor Components in Fast Models
4.1 About the CT processor components
4.2 ARMAEMv8AMPCT component
4.2.1 ARMAEMv8AMPCT - parameters
4.3 ARMCortexA57xnCT component
4.3.1 ARMCortexA57xnCT - about
4.3.2 ARMCortexA57xnCT - ports
4.3.3 ARMCortexA57xnCT - parameters
4.3.4 ARMCortexA57xnCT - registers
4.3.5 ARMCortexA57xnCT - caches
4.3.6 ARMCortexA57xnCT - debug features
4.3.7 ARMCortexA57xnCT - verification and testing
4.3.8 ARMCortexA57xnCT - differences between the CT model and RTL implementations
4.4 ARMCortexA53xnCT component
4.4.1 ARMCortexA53xnCT - about
4.4.2 ARMCortexA53xnCT - ports
4.4.3 ARMCortexA53xnCT - parameters
4.4.4 ARMCortexA53xnCT - registers
4.4.5 ARMCortexA53xnCT - caches
4.4.6 ARMCortexA53xnCT - debug features
4.4.7 ARMCortexA53xnCT - verification and testing
4.4.8 ARMCortexA53xnCT - differences between the CT model and RTL implementations
4.5 ARMCortexA17xnCT component
4.5.1 ARMCortexA17xnCT - about
4.5.2 ARMCortexA17xnCT - ports
4.5.3 ARMCortexA17xnCT - parameters
4.6 ARMCortexA15xnCT component
4.6.1 ARMCortexA15xnCT - about
4.6.2 ARMCortexA15xnCT - ports
4.6.3 ARMCortexA15xnCT - parameters
4.6.4 ARMCortexA15xnCT - registers
4.6.5 ARMCortexA15xnCT - caches
4.6.6 ARMCortexA15xnCT - debug features
4.6.7 ARMCortexA15xnCT - verification and testing
4.6.8 ARMCortexA15xnCT - differences between the CT model and RTL implementations
4.7 ARMCortexA12xnCT component
4.7.1 ARMCortexA12xnCT - about
4.7.2 ARMCortexA12xnCT - ports
4.7.3 ARMCortexA12xnCT - parameters
4.7.4 ARMCortexA12xnCT - registers
4.7.5 ARMCortexA12xnCT - caches
4.7.6 ARMCortexA12xnCT - debug features
4.7.7 ARMCortexA12xnCT - verification and testing
4.7.8 ARMCortexA12xnCT - differences between the CT model and RTL implementations
4.8 ARMCortexA9MPxnCT component
4.8.1 ARMCortexA9MPxnCT - about
4.8.2 ARMCortexA9MPxnCT - ports
4.8.3 ARMCortexA9MPxnCT - parameters
4.8.4 ARMCortexA9MPxnCT - registers
4.8.5 ARMCortexA9MPxnCT - caches
4.8.6 ARMCortexA9MPxnCT - debug features
4.8.7 ARMCortexA9MPxnCT - verification and testing
4.8.8 ARMCortexA9MPxnCT - differences between the CT model and RTL implementations
4.9 ARMCortexA9UPCT component
4.9.1 ARMCortexA9UPCT - about
4.9.2 ARMCortexA9UPCT - ports
4.9.3 ARMCortexA9UPCT - parameters
4.9.4 ARMCortexA9UPCT - registers
4.9.5 ARMCortexA9UPCT - caches
4.9.6 ARMCortexA9UPCT - debug features
4.9.7 ARMCortexA9UPCT - verification and testing
4.9.8 ARMCortexA9UPCT - differences between the CT model and RTL implementations
4.10 ARMCortexA8CT component
4.10.1 ARMCortexA8CT - about
4.10.2 ARMCortexA8CT - ports
4.10.3 ARMCortexA8CT - parameters
4.10.4 ARMCortexA8CT - registers
4.10.5 ARMCortexA8CT - caches
4.10.6 ARMCortexA8CT - debug features
4.10.7 ARMCortexA8CT - verification and testing
4.10.8 ARMCortexA8CT - differences between the CT model and RTL implementations
4.11 ARMCortexA7xnCT component
4.11.1 ARMCortexA7xnCT - about
4.11.2 ARMCortexA7xnCT - ports
4.11.3 ARMCortexA7xnCT - parameters
4.11.4 ARMCortexA7xnCT - registers
4.11.5 ARMCortexA7xnCT - caches
4.11.6 ARMCortexA7xnCT - debug features
4.11.7 ARMCortexA7xnCT - verification and testing
4.11.8 ARMCortexA7xnCT - differences between the CT model and RTL implementations
4.12 ARMCortexA5MPxnCT component
4.12.1 ARMCortexA5MPxnCT - about
4.12.2 ARMCortexA5MPxnCT - ports
4.12.3 ARMCortexA5MPxnCT - parameters
4.12.4 ARMCortexA5MPxnCT - registers
4.12.5 ARMCortexA5MPxnCT - caches
4.12.6 ARMCortexA5MPxnCT - debug features
4.12.7 ARMCortexA5MPxnCT - verification and testing
4.12.8 ARMCortexA5MPxnCT - differences between the CT model and RTL implementations
4.13 ARMCortexA5CT component
4.13.1 ARMCortexA5CT - about
4.13.2 ARMCortexA5CT - ports
4.13.3 ARMCortexA5CT - parameters
4.13.4 ARMCortexA5CT - registers
4.13.5 ARMCortexA5CT - caches
4.13.6 ARMCortexA5CT - debug features
4.13.7 ARMCortexA5CT - verification and testing
4.13.8 ARMCortexA5CT - differences between the CT model and RTL implementations
4.14 ARMCortexR7MPxnCT component
4.14.1 ARMCortexR7MPxnCT - about
4.14.2 ARMCortexR7MPxnCT - ports
4.14.3 ARMCortexR7MPxnCT - parameters
4.14.4 ARMCortexR7MPxnCT - registers
4.14.5 ARMCortexR7MPxnCT - caches
4.14.6 ARMCortexR7MPxnCT - debug features
4.14.7 ARMCortexR7MPxnCT - verification and testing
4.14.8 ARMCortexR7MPxnCT - differences between the CT model and RTL implementations
4.15 ARMCortexR5CT component
4.15.1 ARMCortexR5CT - about
4.15.2 ARMCortexR5CT - ports
4.15.3 ARMCortexR5CT - parameters
4.15.4 ARMCortexR5CT - registers
4.15.5 ARMCortexR5CT - caches
4.15.6 ARMCortexR5CT - debug features
4.15.7 ARMCortexR5CT - verification and testing
4.15.8 ARMCortexR5CT - performance
4.15.9 ARMCortexR5CT - differences between the CT model and RTL implementations
4.16 ARMCortexR4CT component
4.16.1 ARMCortexR4CT - about
4.16.2 ARMCortexR4CT - ports
4.16.3 ARMCortexR4CT - parameters
4.16.4 ARMCortexR4CT - registers
4.16.5 ARMCortexR4CT - caches
4.16.6 ARMCortexR4CT - debug features
4.16.7 ARMCortexR4CT - verification and testing
4.16.8 ARMCortexR4CT - performance
4.16.9 ARMCortexR4CT - differences between the CT model and RTL implementations
4.17 ARMCortexM4CT component
4.17.1 ARMCortexM4CT - about
4.17.2 ARMCortexM4CT - ports
4.17.3 ARMCortexM4CT - parameters
4.17.4 ARMCortexM4CT - registers
4.17.5 ARMCortexM4CT - caches
4.17.6 ARMCortexM4CT - debug features
4.17.7 ARMCortexM4CT - verification and testing
4.17.8 ARMCortexM4CT - performance
4.17.9 ARMCortexM4CT - differences between the CT model and RTL implementations
4.18 ARMCortexM3CT component
4.18.1 ARMCortexM3CT - about
4.18.2 ARMCortexM3CT - ports
4.18.3 ARMCortexM3CT - parameters
4.18.4 ARMCortexM3CT - registers
4.18.5 ARMCortexM3CT - caches
4.18.6 ARMCortexM3CT - debug features
4.18.7 ARMCortexM3CT - verification and testing
4.18.8 ARMCortexM3CT - performance
4.18.9 ARMCortexM3CT - differences between the CT model and RTL implementations
4.19 ARM1176CT component
4.19.1 ARM1176CT - about
4.19.2 ARM1176CT - ports
4.19.3 ARM1176CT - parameters
4.19.4 ARM1176CT - registers
4.19.5 ARM1176CT - debug features
4.19.6 ARM1176CT - verification and testing
4.19.7 ARM1176CT - differences between the CT model and RTL implementations
4.20 ARM1136CT component
4.20.1 ARM1136CT - about
4.20.2 ARM1136CT - ports
4.20.3 ARM1136CT - parameters
4.20.4 ARM1136CT - registers
4.20.5 ARM1136CT - debug features
4.20.6 ARM1136CT - verification and testing
4.20.7 ARM1136CT - differences between the CT model and RTL implementations
4.21 ARM968CT component
4.21.1 ARM968CT - about
4.21.2 ARM968CT - ports
4.21.3 ARM968CT - parameters
4.21.4 ARM968CT - registers
4.21.5 ARM968CT - debug features
4.21.6 ARM968CT - verification and testing
4.21.7 ARM968CT - performance
4.21.8 ARM968CT - DMA
4.22 ARM926CT component
4.22.1 ARM926CT - about
4.22.2 ARM926CT - ports
4.22.3 ARM926CT - parameters
4.22.4 ARM926CT - registers
4.22.5 ARM926CT - debug features
4.22.6 ARM926CT - verification and testing
4.22.7 ARM926CT - differences between the CT model and RTL implementations
5 Peripheral and Interface Components in Fast Models
5.1 Peripheral and interface components - about
5.2 AMBA-PV components
5.2.1 AMBA-PV components - about
5.2.2 PVBus2AMBAPV component
5.2.3 AMBAPV2PVBus component
5.2.4 PVBus2AMBAPVACE component
5.2.5 AMBAPVACE2PVBus component
5.2.6 SGSignal2AMBAPVSignal component
5.2.7 AMBAPVSignal2SGSignal component
5.2.8 SGStateSignal2AMBAPVSignalState component
5.2.9 AMBAPVSignalState2SGStateSignal component
5.2.10 SGValue2AMBAPVValue component
5.2.11 SGValue2AMBAPVValue64 component
5.2.12 AMBAPVValue2SGValue component
5.2.13 AMBAPVValue2SGValue64 component
5.2.14 SGValueState2AMBAPVValueState component
5.2.15 SGValueState2AMBAPVValueState64 component
5.2.16 AMBAPVValueState2SGValueState component
5.2.17 AMBAPVValueState2SGValueState64 component
5.3 Clocking components
5.3.1 Clocking components - about
5.3.2 ClockDivider component
5.3.3 ClockTimer component
5.3.4 ClockTimer64 component
5.3.5 MasterClock component
5.4 Peripheral components
5.4.1 AndGate component
5.4.2 AudioOut_File component
5.4.3 AudioOut_SDL component
5.4.4 BP135_AXI2APB component
5.4.5 BP141_TZMA component
5.4.6 BP147_TZPC component
5.4.7 CCI400 component
5.4.8 DMC_400 component
5.4.9 ElfLoader component
5.4.10 FlashLoader component
5.4.11 GenericTimer component
5.4.12 GIC_400 component
5.4.13 GIC500Distributor component
5.4.14 GICv3Distributor component
5.4.15 HostBridge component
5.4.16 ICS307 component
5.4.17 IntelStrataFlashJ3 component
5.4.18 MemoryMappedCounterModule component
5.4.19 MemoryMappedGenericWatchdog component
5.4.20 MessageBox component
5.4.21 MMC component
5.4.22 MMU_400 component
5.4.23 MMU_500 component
5.4.24 OrGate component
5.4.25 PL011_Uart component
5.4.26 PL022_SSP component
5.4.27 PL030_RTC component
5.4.28 PL031_RTC component
5.4.29 PL041_AACI component
5.4.30 PL050_KMI component
5.4.31 PL061_GPIO component
5.4.32 PL080_DMAC component
5.4.33 PL110_CLCD component
5.4.34 PL111_CLCD component
5.4.35 PL180_MCI component
5.4.36 PL192_VIC component
5.4.37 PL310_L2CC component
5.4.38 PL330_DMAC component
5.4.39 PL340_DMC component
5.4.40 PL350_SMC component
5.4.41 PL350_SMC_NAND_FLASH component
5.4.42 PL370_HDLCD component
5.4.43 PL390_GIC component
5.4.44 PowerController component
5.4.45 PS2Keyboard component
5.4.46 PS2Mouse component
5.4.47 RAMDevice component
5.4.48 RemapDecoder component
5.4.49 SerialCrossover component
5.4.50 SMSC_91C111 component
5.4.51 SP804_Timer component
5.4.52 SP805_Watchdog component
5.4.53 SP810_SysCtrl component
5.4.54 TelnetTerminal component
5.4.55 TZC_400 component
5.4.56 TZIC component
5.4.57 v8EmbeddedCrossTrigger_Interface component
5.4.58 v8EmbeddedCrossTrigger_Matrix component
5.4.59 VFS2 component
5.4.60 VirtioBlockDevice component
5.4.61 VirtualEthernetCrossover component
5.5 PVBus components
5.5.1 About PVBus components
5.5.2 About PVBus system components
5.5.3 PVBus Transaction Master ID
5.5.4 PVBus examples
5.5.5 PVBusDecoder component
5.5.6 PVBusMaster component
5.5.7 PVBusRange component
5.5.8 PVBusSlave component
5.5.9 TZSwitch component
5.5.10 Labeller and LabellerForDMA330 components
5.5.11 PVBus C++ transaction and Tx_Result classes
5.6 Visualisation Library
5.6.1 Visualisation Library - about
5.6.2 LISA Visualisation models
5.6.3 GUIPoll component
5.6.4 Visualisation Library C++ classes
6 Base Platform: Platform and Components
6.1 About the Base Platform
6.2 Base Platform - memory
6.2.1 Base Platform - secure memory
6.2.2 Base Platform - memory map
6.2.3 Base Platform - DRAM
6.3 Base Platform - interrupt assignments
6.4 Base Platform - clocks
6.5 Base platform - parameters
6.6 Base Platform - components
6.6.1 Components - about
6.6.2 DebugAccessPort component
6.6.3 Simulator visualization component
6.6.4 VE_SysRegs component
6.7 Base Platform - VE compatibility
6.7.1 Base Platform - VE compatibility - GICv2
6.7.2 Base Platform - VE compatibility - GICv3
6.7.3 Base Platform - VE compatibility - system global counter
6.7.4 Base Platform - VE compatibility - disable security
6.8 Base Platform - unsupported VE features
6.8.1 Base Platform - unsupported VE features - memory aliasing at 0x08_00000000
6.8.2 Base Platform - unsupported VE features - boot ROM alias at 0x00_0800_0000
6.8.3 Base Platform - unsupported VE features - change of older parameters
7 Emulation Baseboard Model: Platform and Components
7.1 About the Emulation Baseboard components
7.2 EB memory map
7.3 EB parameters
7.3.1 EB instantiation parameters
7.3.2 EB switch S6
7.3.3 EB switch S8
7.4 EBVisualisation component
7.4.1 EBVisualisation - about
7.4.2 EBVisualisation - ports
7.4.3 EBVisualisation - parameters
7.4.4 EBVisualisation - verification and testing
7.4.5 EBVisualisation - performance
7.4.6 EBVisualisation - library dependencies
7.5 EB_SysRegs component
7.5.1 EB_SysRegs - about
7.5.2 EB_SysRegs - ports
7.5.3 EB_SysRegs - parameters
7.5.4 EB_SysRegs - registers
7.5.5 EB_SysRegs - verification and testing
7.6 EBCortexA9_SysRegs component
7.6.1 EBCortexA9_SysRegs - about
7.6.2 EBCortexA9_SysRegs - ports
7.6.3 EBCortexA9_SysRegs - registers
7.6.4 EBCortexA9_SysRegs - verification and testing
7.7 TSC2200 component
7.7.1 TSC2200 - about
7.7.2 TSC2200 - ports
7.7.3 TSC2200 - parameters
7.7.4 TSC2200 - verification and testing
7.7.5 TSC2200 - functionality
7.8 Other EB components
7.8.1 EBConnector and EBSocket components
7.8.2 EBInterruptForwarder component
7.8.3 EBRemapper component
7.9 Differences between the EB hardware and the system model
7.9.1 EB hardware features absent
7.9.2 EB hardware features different
7.9.3 Remapping and DRAM aliasing
7.9.4 Status and system control registers
7.9.5 EB FVP PrimeCell Generic Interrupt Controller (PL390)
7.9.6 GPIO2
7.9.7 Timing considerations for the EB FVPs
8 Microcontroller Prototyping System: Platform and Components
8.1 About the Microcontroller Prototyping System components
8.2 MPS memory map
8.2.1 Overview of MPS memory map
8.2.2 MPS registers
8.3 MPSVisualisation component
8.3.1 MPSVisualisation - about
8.3.2 MPSVisualisation - ports
8.3.3 MPSVisualisation - parameters
8.3.4 MPSVisualisation - verification and testing
8.3.5 MPSVisualisation - performance
8.3.6 MPSVisualisation - library dependencies
8.4 MPS_CharacterLCD component
8.4.1 MPS_CharacterLCD - about
8.4.2 MPS_CharacterLCD - ports
8.4.3 MPS_CharacterLCD - registers
8.4.4 MPS_CharacterLCD - verification and testing
8.4.5 MPS_CharacterLCD - performance
8.4.6 MPS_CharacterLCD - library dependencies
8.5 MPS_DUTSysReg component
8.5.1 MPS_DUTSysReg - about
8.5.2 MPS_DUTSysReg - ports
8.5.3 MPS_DUTSysReg - parameters
8.5.4 MPS_DUTSysReg - registers
8.5.5 MPS_DUTSysReg - verification and testing
8.6 Other MPS components
8.6.1 MPSInterruptForwarder and MPSInterruptReceiver components
8.7 Differences between the MPS hardware and the system model
8.7.1 MPS hardware features different
8.7.2 Timing considerations for the MPS FVPs
9 Versatile Express Model: Platform and Components
9.1 About the Versatile Express baseboard components
9.2 VE memory map for Cortex-A series
9.3 VE memory map for Cortex-R series
9.4 VE parameters
9.4.1 VE instantiation parameters
9.4.2 VE secure memory parameters
9.4.3 VE switch S6
9.5 VEVisualisation component
9.5.1 VEVisualisation - about
9.5.2 VEVisualisation - ports
9.5.3 VEVisualisation - parameters
9.5.4 VEVisualisation - verification and testing
9.5.5 VEVisualisation - performance
9.5.6 VEVisualisation - library dependencies
9.6 VE_SysRegs component
9.6.1 VE_SysRegs - about
9.6.2 VE_SysRegs - ports
9.6.3 VE_SysRegs - parameters
9.6.4 VE_SysRegs - registers
9.6.5 VE_SysRegs - verification and testing
9.7 Other VE components
9.7.1 VEConnector and VESocket components
9.7.2 VEInterruptForwarder component
9.7.3 VERemapper component
9.8 Differences between the VE hardware and the system model
9.8.1 Memory map
9.8.2 Memory aliasing
9.8.3 VE hardware features absent
9.8.4 VE hardware features different
9.8.5 Restrictions on the processor models
9.8.6 Timing considerations for the VE FVPs

Release Information

Document History
Issue Date Confidentiality Change
A 31 May 2014 Non-Confidential New document for Fast Models v9.0 based on DUI0423Q for v8.3.
B 30 November 2014 Non-Confidential Update for v9.1.

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