Fast Models Reference Manual

Version 9.5


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Other information
1 Introduction
1.1 About the models
1.2 Model capabilities
1.3 Fast Models accuracy
1.3.1 How accurate are Fast Models?
1.3.2 Timing accuracy of Fast Models
1.3.3 Bus traffic in Fast Models
1.3.4 Instruction prefetch in Fast Models
1.3.5 Out-of-order execution and write-buffers in Fast Models
1.3.6 Caches in Fast Models
1.3.7 Global exclusive monitor in Fast Models
1.4 Processor implementation
1.4.1 Caches in PV models
1.4.2 GICv3 in PV models
1.4.3 CP14 Debug coprocessor
1.4.4 MicroTLBs
1.4.5 TLBs in PV models
1.4.6 Memory access in PV models
1.4.7 Timing in PV models
1.4.8 VIC ports in PV models
1.5 Processor CADI implementation
1.6 CADI interactions with processor behavior
1.7 CADI sync watchpoints
1.8 Non-CADI sync watchpoints
1.8.1 syncLevel definitions
1.8.2 Controlling and observing the syncLevel
1.9 SCADI
1.9.1 About SCADI
1.9.2 Intended uses of CADI and SCADI
1.9.3 Responsibilities of the SCADI caller
1.9.4 SCADI interface access
1.9.5 SCADI semantics
1.10 Checkpoints
1.11 Use of the TelnetTerminal
1.12 Installing Telnet on Microsoft Windows
1.13 Network set up
1.13.1 User mode networking
1.13.2 TAP/TUN networking
2 Protocols
2.1 AMBA-PV protocols
2.1.1 AMBA-PV protocols - about
2.1.2 AMBAPV protocol
2.1.3 AMBAPVACE protocol
2.1.4 AMBAPVSignal protocol
2.1.5 AMBAPVSignalState protocol
2.1.6 AMBAPVValue protocol
2.1.7 AMBAPVValue64 protocol
2.1.8 AMBAPVValueState protocol
2.1.9 AMBAPVValueState64 protocol
2.2 Clocking protocols
2.2.1 Clocking protocols - about
2.2.2 ClockRateControl protocol
2.2.3 TimerCallback protocol
2.2.4 TimerCallback64 protocol
2.2.5 TimerControl protocol
2.2.6 TimerControl64 protocol
2.3 Debug interface protocols
2.3.1 Debug interface protocols - about
2.3.2 CADIDisassemblerProtocol protocol
2.3.3 CADIProtocol protocol
2.4 Peripheral protocols
2.4.1 AudioControl protocol
2.4.2 CharacterLCD protocol
2.4.3 FlashLoaderPort protocol
2.4.4 GUIPollCallback protocol
2.4.5 ICS307Configuration protocol
2.4.6 KeyboardStatus protocol
2.4.7 LCD protocol
2.4.8 LCDLayoutInfo protocol
2.4.9 MMC_Protocol protocol
2.4.10 MouseStatus protocol
2.4.11 PL080_DMAC_DmaPortProtocol protocol
2.4.12 PS2Data protocol
2.4.13 PVBusSlaveControl protocol
2.4.14 PVDevice protocol
2.4.15 PVTransactionMaster protocol
2.4.16 SerialData protocol
2.4.17 TZFilterControl protocol
2.4.18 VirtualEthernet protocol
2.5 Processor protocols
2.5.1 CounterInterface protocol
2.5.2 GICv3Comms protocol
2.5.3 InstructionCount protocol
2.5.4 v8EmbeddedCrossTrigger_controlprotocol protocol
2.6 Signaling protocols
2.6.1 Signaling protocols - about
2.6.2 Signal protocol
2.6.3 StateSignal protocol
2.6.4 Value protocol
2.6.5 Value_64 protocol
2.6.6 ValueState protocol
3 Processor Components
3.1 About the processor components
3.2 Cortex-A processor components
3.2.1 ARMCortexA72xnCT component
3.2.2 ARMAEMv8AMPCT component
3.2.3 ARMCortexA57xnCT component
3.2.4 ARMCortexA53xnCT component
3.2.5 ARMCortexA17xnCT component
3.2.6 ARMCortexA15xnCT component
3.2.7 ARMCortexA12xnCT component
3.2.8 ARMCortexA9MPxnCT component
3.2.9 ARMCortexA9UPCT component
3.2.10 ARMCortexA8CT component
3.2.11 ARMCortexA7xnCT component
3.2.12 ARMCortexA5MPxnCT component
3.2.13 ARMCortexA5CT component
3.3 Cortex-R processor components
3.3.1 ARMCortexR7MPxnCT component
3.3.2 ARMCortexR5CT component
3.3.3 ARMCortexR4CT component
3.4 Cortex-M processor components
3.4.1 ARMCortexM7CT component
3.4.2 ARMCortexM4CT component
3.4.3 ARMCortexM3CT component
3.4.4 ARMCortexM0PlusCT component
3.4.5 ARMCortexM0CT component
3.5 Classic processor components
3.5.1 ARM1176CT component
3.5.2 ARM1136CT component
3.5.3 ARM968CT component
3.5.4 ARM926CT component
4 Peripheral and Interface Components
4.1 Peripheral and interface components - about
4.2 AMBA-PV components
4.2.1 AMBA-PV components - about
4.2.2 PVBus2AMBAPV component
4.2.3 AMBAPV2PVBus component
4.2.4 PVBus2AMBAPVACE component
4.2.5 AMBAPVACE2PVBus component
4.2.6 SGSignal2AMBAPVSignal component
4.2.7 AMBAPVSignal2SGSignal component
4.2.8 SGStateSignal2AMBAPVSignalState component
4.2.9 AMBAPVSignalState2SGStateSignal component
4.2.10 SGValue2AMBAPVValue component
4.2.11 SGValue2AMBAPVValue64 component
4.2.12 AMBAPVValue2SGValue component
4.2.13 AMBAPVValue2SGValue64 component
4.2.14 SGValueState2AMBAPVValueState component
4.2.15 SGValueState2AMBAPVValueState64 component
4.2.16 AMBAPVValueState2SGValueState component
4.2.17 AMBAPVValueState2SGValueState64 component
4.3 Clocking components
4.3.1 Clocking components - about
4.3.2 ClockDivider component
4.3.3 ClockTimer component
4.3.4 ClockTimer64 component
4.3.5 MasterClock component
4.4 Peripheral components
4.4.1 AndGate component
4.4.2 AudioOut_File component
4.4.3 AudioOut_SDL component
4.4.4 BP135_AXI2APB component
4.4.5 BP141_TZMA component
4.4.6 BP147_TZPC component
4.4.7 CCI400 component
4.4.8 CCI500 component
4.4.9 CCN502 component
4.4.10 CCN504 component
4.4.11 CCN508 component
4.4.12 CCN512 component
4.4.13 DMC_400 component
4.4.14 DP500 component
4.4.15 DP550 component
4.4.16 ElfLoader component
4.4.17 FlashLoader component
4.4.18 GenericTimer component
4.4.19 GIC_400 component
4.4.20 GIC500Distributor component
4.4.21 GICv3Distributor component
4.4.22 HostBridge component
4.4.23 ICS307 component
4.4.24 IntelStrataFlashJ3 component
4.4.25 MemoryMappedCounterModule component
4.4.26 MemoryMappedGenericWatchdog component
4.4.27 MessageBox component
4.4.28 MMC component
4.4.29 MMU_400 component
4.4.30 MMU_500 component
4.4.31 OrGate component
4.4.32 PL011_Uart component
4.4.33 PL022_SSP component
4.4.34 PL030_RTC component
4.4.35 PL031_RTC component
4.4.36 PL041_AACI component
4.4.37 PL050_KMI component
4.4.38 PL061_GPIO component
4.4.39 PL080_DMAC component
4.4.40 PL110_CLCD component
4.4.41 PL111_CLCD component
4.4.42 PL180_MCI component
4.4.43 PL192_VIC component
4.4.44 PL310_L2CC component
4.4.45 PL330_DMAC component
4.4.46 PL340_DMC component
4.4.47 PL350_SMC component
4.4.48 PL350_SMC_NAND_FLASH component
4.4.49 PL370_HDLCD component
4.4.50 PL390_GIC component
4.4.51 PS2Keyboard component
4.4.52 PS2Mouse component
4.4.53 RAMDevice component
4.4.54 RemapDecoder component
4.4.55 SerialCrossover component
4.4.56 SMSC_91C111 component
4.4.57 SP804_Timer component
4.4.58 SP805_Watchdog component
4.4.59 SP810_SysCtrl component
4.4.60 TelnetTerminal component
4.4.61 TZC_400 component
4.4.62 TZIC component
4.4.63 v8EmbeddedCrossTrigger_Interface component
4.4.64 v8EmbeddedCrossTrigger_Matrix component
4.4.65 VFS2 component
4.4.66 VirtioBlockDevice component
4.4.67 VirtioP9Device component
4.4.68 VirtualEthernetCrossover component
4.5 PVBus components
4.5.1 About PVBus components
4.5.2 About PVBus system components
4.5.3 PVBus Transaction Master ID
4.5.4 PVBus examples
4.5.5 PVBusDecoder component
4.5.6 PVBusMapper component
4.5.7 PVBusMaster component
4.5.8 PVBusRange component
4.5.9 PVBusSlave component
4.5.10 TZSwitch component
4.5.11 Labeller and LabellerForDMA330 components
4.5.12 PVBus C++ transaction and Tx_Result classes
4.6 Visualisation Library
4.6.1 Visualisation Library - about
4.6.2 LISA Visualisation models
4.6.3 GUIPoll component
4.6.4 Visualisation Library C++ classes
5 Base Platform
5.1 Base - about
5.2 Base - memory
5.2.1 Base - secure memory
5.2.2 Base - memory map
5.2.3 Base - DRAM
5.3 Base - interrupt assignments
5.4 Base - clocks
5.5 Base - parameters
5.6 Base - components
5.6.1 Base - components - about
5.6.2 Base - Base_PowerController component
5.6.3 Base - DebugAccessPort component
5.6.4 Base - simulator visualization component
5.6.5 Base - VE_SysRegs component
5.7 Base - differences between the AEMv8-A FVP and core FVPs
5.8 Base - VE compatibility
5.8.1 Base - VE compatibility - GICv2
5.8.2 Base - VE compatibility - GICv3
5.8.3 Base - VE compatibility - system global counter
5.8.4 Base - VE compatibility - disable security
5.9 Base - unsupported VE features
5.9.1 Base - unsupported VE features - memory aliasing at 0x08_00000000
5.9.2 Base - unsupported VE features - boot ROM alias at 0x00_0800_0000
5.9.3 Base - unsupported VE features - change of older parameters
6 Microcontroller Prototyping System 2
6.1 MPS2 - about
6.2 MPS2 - memory maps
6.2.1 MPS2 - memory map for models without the ARMv8-M additions
6.2.2 MPS2 - memory map for models with the ARMv8-M additions
6.3 MPS2 - interrupt assignments
6.4 MPS2 - differences between models and hardware
7 Versatile Express Model
7.1 About the Versatile Express baseboard components
7.2 VE memory map for Cortex-A series
7.3 VE memory map for Cortex-R series
7.4 VE parameters
7.4.1 VE instantiation parameters
7.4.2 VE secure memory parameters
7.4.3 VE switch S6
7.5 VEVisualisation component
7.5.1 VEVisualisation - about
7.5.2 VEVisualisation - ports
7.5.3 VEVisualisation - parameters
7.5.4 VEVisualisation - verification and testing
7.5.5 VEVisualisation - performance
7.5.6 VEVisualisation - library dependencies
7.6 VE_SysRegs component
7.6.1 VE_SysRegs - about
7.6.2 VE_SysRegs - ports
7.6.3 VE_SysRegs - parameters
7.6.4 VE_SysRegs - registers
7.6.5 VE_SysRegs - verification and testing
7.7 Other VE components
7.7.1 VEConnector and VESocket components
7.7.2 VEInterruptForwarder component
7.7.3 VERemapper component
7.8 Differences between the VE hardware and the system model
7.8.1 Memory map
7.8.2 Memory aliasing
7.8.3 VE hardware features absent
7.8.4 VE hardware features different
7.8.5 Restrictions on the processor models
7.8.6 Timing considerations for the VE FVPs

Release Information

Document History
Issue Date Confidentiality Change
A 31 May 2014 Non-Confidential New document for Fast Models v9.0, from DUI0423Q for v8.3.
B 30 November 2014 Non-Confidential Update for v9.1.
C 28 February 2015 Non-Confidential Update for v9.2.
D 31 May 2015 Non-Confidential Update for v9.3.
E 31 August 2015 Non-Confidential Update for v9.4.
F 30 November 2015 Non-Confidential Update for v9.5.

Non-Confidential Proprietary Notice

This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.
Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents.
THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, ARM makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights.
This document may include technical inaccuracies or typographical errors.
TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to ARM’s customers is not intended to create or refer to any partnership relationship with any other company. ARM may make changes to this document at any time and without notice.
If any of the provisions contained in these terms conflict with any of the provisions of any signed written agreement covering this document with ARM, then the signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail.
Copyright © [2014, 2015], ARM Limited or its affiliates. All rights reserved.
ARM Limited. Company 02557590 registered in England.
110 Fulbourn Road, Cambridge, England CB1 9NJ.
LES-PRE-20349

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.
Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is Final, that is for a developed product.

Web Address

Non-ConfidentialPDF file icon PDF versionARM DUI0834F
Copyright © 2014, 2015 ARM. All rights reserved.