5.4.5 FVP_VE_Cortex-A15xn CoreTile component

This section describes the FVP_VE_Cortex-A15xn CoreTile component.

FVP_VE_Cortex-A15xn CoreTile - parameters

These components have instantiation-time parameters, which you can change when you start the models, where x = 1, 2, 4.

This CoreTile FVP is based on revision 2, patch 0 (r2p0) of the Cortex-A15 cluster.
The syntax to use in a configuration file is:
cluster.parameter=value

Table 5-20 FVP_VE_Cortex-A15xn CoreTile parameters

Parameter Type Allowed values Default value Description
CFGSDISABLE bool true, false false Disable some accesses to DIC registers.
CLUSTER_ID int 0-15 0 Cluster ID value.
IMINLN bool true, false true Instruction cache minimum line size: false = 32 bytes, true = 64 bytes.
PERIPHBASE int - 0x13080000a Base address of peripheral memory space.
dic-spi_count int 0-224, in increments of 32 64 Number of shared peripheral interrupts implemented.
internal_vgic bool true, false true Configures whether the model of the cluster contains a Virtual Generic Interrupt Controller (VGIC).
l1_dcache-state_modelled bool true, false false Set whether L1 D-cache has stateful implementation.
l1_icache-state_modelled bool true, false false Set whether L1 I-cache has stateful implementation.
l2_cache-size int 0x080000, 0x100000, 0x200000, 0x400000. 0x400000 Set L2 cache size in bytes.
l2_cache-state_modelled bool true, false false Set whether L2 cache has stateful implementation.
l2-data-slice int 0, 1, 2 0 L2 data RAM slice.
l2-tag-slice int 0, 1 0 L2 tag RAM slice.
The FVP_VE_Cortex-A15MPx1 has the PERIPHBASE parameter set to 0x1F000000, which is the base address of peripheral memory space on VE hardware.
The parameters for each Cortex-A15 core are set individually. Each core has its own timer and watchdog.
The syntax to use in a configuration file is:
cluster.cpu[n].parameter=value
where n is the core number, from 0-3 inclusive.

Table 5-21 FVP_VE_Cortex-A15xn CoreTile parameters - individual cores

Parameter Type Allowed values Default value Description
CFGEND bool true, false false Initialize to BE8 endianness.
CP15SDISABLE bool true, false false Initialize to disable access to some CP15 registers.
DBGROMADDR int 0x12000003 0x12000003 This value is used to initialize the CP15 DBGDRAR register. Bits[39:12] of this register specify the ROM table physical address.
DBGROMADDRV bool true, false true true sets bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid.
DBGSELFADDR int 0x00010003 0x00010003 This value is used to initialize the CP15 DBGDSAR register. Bits[39:17] of this register specify the ROM table physical address.
DBGSELFADDRV bool true, false true true sets bits[1:0] of the CP15 DBGDSAR to indicate that the address is valid.
TEINIT bool true, false false T32 exception enable. The default has exceptions including reset handled in A32 state.
VINITHI bool true, false false Initialize with high vectors enabled.
ase-presentb bool true, false true Set whether core model has been built with NEON™ support.
min_sync_level int 0-3 0 Controls the minimum syncLevel by the CADI parameter interface.
semihosting-cmd_line string No limit except memory '' Command line available to semihosting SVC calls.
semihosting-cwd string - - Virtual address of CWD.
semihosting-enable bool true, false true Enable semihosting SVC traps.
semihosting-ARM_SVC int 0x000000-0xFFFFFF 0x123456 A32 SVC number for semihosting.
semihosting-Thumb_SVC int 0x00-0xFF 0xAB T32 SVC number for semihosting.
semihosting-heap_base int 0x00000000-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit int 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of top of heap.
semihosting-stack_base int 0x00000000-0xFFFFFFFF 0x10000000 Virtual address of base of descending stack.
semihosting-stack_limit int 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of stack limit.
vfp-enable_at_resetc bool true, false false Enable coprocessor access and VFP at reset.
vfp-presentb bool true, false true Set whether processor model has been built with VFP support.
a
If you are using the ARMCortexA15xnCT component on a VE model platform, this parameter is set automatically to 0x1F000000 and is not visible in the parameter list.
b 
The ase-present and vfp-present parameters configure the synthesis options for the Cortex-A15 model. The options are:
vfp present and ase present
NEON and VFPv3-D32 supported.
vfp present and ase not present
VFPv3-D16 supported.
vfp not present and ase present
Illegal. Forces vfp-present to true so model has NEON and VFPv3-D32 support.
vfp not present and ase not present
NEON and VFPv3-D32 not supported.
c
This model-specific behavior has no hardware equivalent.
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