Figure 2-1 CLCD window in its default state at startup
The top section of the CLCD window displays the status information.
Eight white boxes show the state of the VE User DIP switches:
These represent switch S6 on the VE hardware, USERSW[8:1], which is
mapped to bits [7:0] of the SYS_SW register at address
The switches are in the off position by default. To change its state,
click in the area above or below a white box.
Eight white boxes show the state of the VE Boot DIP switches.
These represent switch S8 on the VE hardware, BOOTSEL[8:1], which is
mapped to bits [15:8] of the SYS_SW register at address
The switches are in the off position by default.
Note ARM recommends that you configure the Boot DIP switches using the
boot_switch model parameter instead of using the CLCD interface.
Changing Boot DIP switch positions while the model is running can result in
Eight colored boxes indicate the state of the VE User LEDs.
These represent LEDs D[21:14] on the VE hardware, which are mapped to
bits [7:0] of the SYS_LED register at address
. The boxes
correspond to the red/yellow/green LEDs on the VE hardware.
- Total Instr
A counter showing the total number of instructions executed.
Because the FVP models provide a Programmer’s View (PV) of the system, the CLCD
displays total instructions rather than total processor cycles. Timing might differ
substantially from the hardware because:
- Bus fabric is simplified.
- Memory latencies are minimized.
- Cycle approximate processor and peripheral models are used.
In general, bus transaction timing is consistent with the hardware,
but the timing of operations within the model is not accurate.
- Total Time
A counter showing the total elapsed time, in seconds.
This time is wall clock time, not simulated time.
- Rate Limit
A feature that disables or enables fast simulation.
Because the system model is highly optimized, your code might run
faster than it would on real hardware. This effect might cause timing issues.
Rate Limit is enabled by default. Simulation time is restricted so that it more
closely matches real time.
To disable or enable Rate Limit, click the square button. When you
disable Rate Limit, the text changes from ON to OFF and the colored box becomes
darker. You can configure this option when instantiating the model with the
rate_limit-enable visualization component parameter.
When you click the Total Instr or
Total Time items in the CLCD, the display changes
to show Instr/sec (instructions per second) and
Perf Index (performance index).
Figure 2-2 CLCD window with Rate Limit ON, showing Instr/sec and Perf Index
You can click the items again to toggle between the original and
The number of instructions that execute per second of wall clock time.
- Perf Index
- The ratio of real time to simulation time. The larger the ratio, the faster the
simulation runs. If you enable the Rate Limit feature, the Perf Index approaches
You can reset the simulation counters by resetting the model.
The VE FVP CLCD displays the core run state for each core with a colored icon. The icons
are to the left of the Total Instr (or
Inst/sec) item. They appear when you start the simulation.
Figure 2-3 Core run state icons for a quad core model
If the CLCD window has focus:
- Any keyboard input is translated to PS/2 keyboard data.
- Any mouse activity over the window is translated into PS/2 relative
mouse motion data. The data is then streamed to the KMI peripheral model FIFOs.
Note The simulator only sends relative mouse motion events to the model. As a
result, the host mouse pointer does not necessarily align with the target OS mouse pointer.
You can hide the host mouse pointer by pressing the left
Ctrl+left Alt keys. Press the keys again to redisplay
the host mouse pointer. Only the left Ctrl key is operational. The
right Ctrl key does not have the same effect.
If you prefer to use a different key, configure it with the
visualization component parameter.