5.5.5 VE - restrictions on processor models

General restrictions apply to the Fixed Virtual Platform (FVP) implementations of ARM processors.

  • The simulator does not model cycle timing. In aggregate, all instructions execute in one processor master clock cycle, except for Wait For Interrupt.
  • Write buffers are not modeled, except in AEMs.
  • Most aspects of TLB behavior are implemented in the models. In ARMv7 models, and later ones, the TLB memory attribute settings are used when stateful cache is enabled.
  • No device-accurate MicroTLB is implemented.
  • A single memory access port is implemented. The port combines accesses for instruction, data, DMA, and peripherals. Configuration of the peripheral port memory map register is ignored.
  • All memory accesses are atomic and are performed in Programmer’s View (PV) order. All transactions on the PVBus are a maximum of 64 bits wide. Unaligned accesses are always performed as byte transfers.
  • Some instruction sequences are executed atomically, ahead of the component master clock, so that system time does advance during their execution. This change can affect sequential access of device registers where devices are expecting time to move on between each access.
  • Interrupts are not taken at every instruction boundary.
  • Integration and test registers are not implemented.
  • Not all CP14 debug registers are implemented on all processors.
  • Breakpoint types that the model supports directly are:
    • Single address unconditional instruction breakpoints.
    • Single address unconditional data breakpoints.
    • Unconditional instruction address range breakpoints.
  • Pseudoregisters in the debugger support processor exception breakpoints. Setting an exception register to a nonzero value stops execution on entry to the associated exception vector.
  • Performance counters are not implemented on all models.
The following restrictions apply to the FVP implementation of a Cortex-A9 MPCore cluster:
  • The Cortex-A9MPCore cluster contains some memory-mapped peripherals. The FVP models them.
  • The model cluster sees two 4GB address spaces, one as seen from Secure mode and one as seen from Normal mode. The address spaces contain zero-wait state memory and peripherals, but much of the space is unmapped.
  • The RR bit in the SCTLR is ignored.
  • The Power Control Register in the system control coprocessor is implemented but writing to it does not change the behavior of the model.
  • The SCU is only partially modeled:
    • The SCU enable bit is ignored. The SCU is always enabled.
    • The SCU ignores the invalidate-all register.
    • A memory write followed by a read to refill from memory represents coherency operations, rather than using cache-to-cache transfers.
    • There is no address filtering within the SCU. The enable bit for this feature is ignored.
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