This section describes the features of the hardware that the models do not implement, or implement with significant differences.
MPS2 implements most devices. Some peripherals have minimal
- The Ethernet module in the model is a LAN91C111. The hardware
documents specify a LAN9220.
- The Audio module is RAZ/WI.
- The STMPE811 touchscreen module only reports touch
- The model of the Ampire LCD module supports a subset of the
You can display images and text on an emulated VGA output, images on
the LCD, and text on the UART.
The model implements an Implementation Defined
Attribution Unit (IDAU) inside each core. The top-level component
coordinates the IDAU implementations by passing down parameters. In contrast, the
MPS2 specification [ARMv8-M MPS2 System Specification
(ARM-ECM-0468897), v0.8] has a common, system level IDAU, which all cores and
various devices use.
You cannot reprogram the IDAUs of the model. The model only reads the
Secure Controller Register Block register, NSC_CFG. Set it using the top-level
parameters, NSC_CFG_0 and NSC_CFG_1 (corresponding to bits 0 and 1 of NSC_CFG,
The model does not have the random number generator or unique
ID/secure storage of the MPS2 specification.
The model does not support MTB, ETM, and TPIU. MTB RAM is absent.
In the Memory Gating Unit, the model provides a configurable block
size. For performance reasons, the minimum block size in the model is 4096 bytes.
Hardware and later models might allow smaller block sizes. Software must use the
BLK_CFG register to determine block size.
FVPs enable software applications to run in a functionally accurate simulation.
However, because of the relative balance of fast simulation speed over timing
accuracy, there are situations where the models might behave unexpectedly.
If your code interacts with real world devices such as timers and
keyboards, data arrives in the modeled device in real world, or wall clock, time.
However, simulation time can run faster than the wall clock. So, a single key press
might be interpreted as several repeated key presses, or a single mouse click might
be interpreted as a double click.
To avoid this mismatch, the FVPs provide the Rate Limit feature. Enabling Rate Limit forces the
model to run at wall clock time. For interactive applications, ARM recommends
enabling Rate Limit. Use the Rate Limit button in the CLCD display or the
rate_limit-enable model instantiation parameter.