5.4.6 ARMAEMv8AMPCT component

This section describes the ARMv8-A Architecture Envelope Model (AEM) component.

ARMAEMv8AMPCT - parameters

This section describes the parameters that configure the behavior of the AEM ARMv8-A processor model.

ARMAEMv8AMPCT - cluster parameters

This section describes the parameters.

Note:

  • Terms such as cluster might replace cpu on some systems.
  • The parameter PERIPHBASE is locked down in the VE FVP.

Table 5-22 ARMAEMv8AMPCT cluster parameters

Parameter Type Allowed values Default value Description
apsr_read_restrict bool true, false false At EL0, unknown bits of APSR are RAZ.
auxilliary_feature_register0 int

0x0-0xFFFFFFFF

0x0 Value for Auxiliary Feature Register 0 (ID_AFR0).
BPIMVA_causes_translation_lookup bool true, false false Do a translation when BPIMVA instruction is executed. This translation might cause a translation fault.
clear_reg_top_eret int 0x0-0x2 0x1 Clear top 32 bits of general purpose registers on exception return. 0x0 = preserve, 0x1 = clear to zero, 0x2 = random choice of preserve or clear to zero.
delay_serror int

0x0-0xFFFFFFFF

0x0 Minimum propagation delay of the System Error (SERR) signal into the cluster. Accurate in low-latency mode (-C cpu.scheduler_mode=1), but otherwise any delay might be larger.
el0_el1_only_non_secure bool true, false false Controls security state of EL0 and EL1 if EL2 and EL3 are not implemented. true means non-secure.
exercise_stxr_fail bool true, false false When true, return a pseudorandom majority of Store Exclusive Register (STXR) instructions as Failed.
has_16bit_asids bool true, false true Enable 16-bit Address Space IDentifiers (ASIDs).
has_el2 bool true, false true Enable EL2.
has_el3 bool true, false true Enable EL3.
has_delayed_sysreg bool true, false false Delay the functional effect of system register writes until ISB or implicit barrier.
has_writebuffer bool true, false false Implement write access buffering before L1 cache. Might affect ext_abort behavior.
hcr_swio_res1 bool true, false false Whether either HCR.SWIO or HCR_EL2.SWIO, or both are RES1.
is_uniprocessor bool true, false false Value for the U bit in MPIDR. true disables L1 cache coherency protocols.
max_32bit_el int 0x1-0x3 0x3 Maximum exception level supporting AArch32 modes. 0x1 means no support.
MIDR int

0x0-0xFFFFFFFF

0x410FD0F0 Value for Main ID Register (MIDR).
mixed_endian int 0x0-0x2 0x1 Enable the processor to change the endianness at runtime. 0x0 = not supported, 0x1 = supported at all exception levels, 0x2 = supported at EL0 only.
NUM_CORES int 0x0-0x4 0x4 Number of cores implemented.
PA_SIZE int 0x20-0x30 0x28 Physical address size, in bits.
register_reset_data int - 0x0 Fill data for register bits when they become unknown at reset.
scramble_unknowns_at_reset bool true, false true Fill in unknown bits in registers at reset with register_reset_data.
take_ccfail_undef bool true, false true In AArch32, take Undefined Instruction exception even if the instruction fails its condition-codes check.
tidcp_traps_el0_undef_imp_def bool true, false true The TIDCP bit traps, in EL0, undefined implementation defined instructions accessing coprocessor registers.
unpredictable_hvc_behaviour int 0x0-0x1 0x0 Define HVC unpredictable behavior in HYP mode, EL2, when the SCR.HCE bit is clear. 0x0 = Undefined Instruction, 0x1 = NOP instruction.
unpredictable_smc_behaviour int 0x0-0x1 0x0 Define SMC unpredictable behavior in Secure mode, EL3, when the SCR.SCD bit is clear. 0x0 = Undefined Instruction, 0x1 = NOP instruction.
warn_unpredictable_in_v7 bool true, false true Warn of unpredictable behavior in ARMv7.
ARMAEMv8AMPCT - core parameters

This section describes the parameters.

Each core in a cluster has its own parameters. The models use the parameters for cores in sequence, from cpu0 onwards. The models ignore parameters for uninstantiated cores.

Table 5-23 ARMAEMv8AMPCT core parameters

Parameter Type Allowed values Default value Description
cpu[n].CONFIG64 bool true, false true Enable AArch64.
cpu[n].SMPnAMP bool true, false true This core is in the inner shared domain, and uses its cache coherency protocol.
cpu[n].CFGEND bool true, false false Use big-endian order.
cpu[n].CP15SDISABLE bool true, false false Disable access to some CP15 registers in AArch32.
cpu[n].ase-present bool true, false true Enable NEON™.
cpu[n].VINITHI bool true, false false Enable high vectors. Base address 0xFFFF0000.
cpu[n].RVBAR int

0x0-

0xFFFFFFFFFFFC

0x0 Reset Vector Base Address when resetting into AArch64.
cpu[n].vfp-present bool true, false true Enable floating-point arithmetic.
cpu[n].vfp-enable_at_reset bool true, false false Enable coprocessor access and VFP at reset.a
cpu[n].force-fpsid bool true, false false Override the FPSID value.
cpu[n].force-fpsid-value int

0x0-0xFFFFFFFF

0x0 Value for the overridden FPSID.
cpu[n].TEINIT bool true, false false Controls the initial state of SCTLR.TE in AArch32. When set, causes AArch32 exceptions (including reset) to be taken in T32 mode.
cpu[n].etm-present bool true, false true Enable Embedded Trace Macrocell (ETM).
cpu[n].min_sync_level int 0x0-0x3 0x0 Minimum CADI syncLevel. 0 = off, 1 = syncState, 2 = postInsnIO, 3 = postInsnAll.
ARMAEMv8AMPCT - cache parameters

This section describes the parameters.

Table 5-24 ARMAEMv8AMPCT cache parameters

Parameter Type Allowed values Default value Description
cache_maintenance_hits_watchpoints bool true, false false Enable AArch32 cache maintenance by DCIMVAC to trigger watchpoints.b
dcache-state_modelled bool true, false false Stateful implementation, with line allocation in D-caches at all levels.c
icache-state_modelled bool true, false false Stateful implementation, with line allocation in I-caches at all levels.c
memory.l2_cache.is_inner_cacheable bool true, false true L2 cache is inner cacheable, not outer cacheable.
memory.l2_cache.is_inner_shareable bool true, false true L2 cache is inner shareable, not outer shareable.
cache-log2linelen int 0x4-0x8 0x6 Log2(cache-line length, in bytes).
icache-log2linelen int 0x0-0x8 0x0 If non-zero, Log2(instruction cache line length in bytes). Otherwise, use cache-log2linelen.
cpu[n].DCZID-log2-block-size int 0x0-0x9 0x8 Log2(block size) cleared by DC ZVA instruction.d
dcache-size int 0x4000-0x100000 0x8000 L1 D-cache size, in bytes.
dcache-ways int 0x1-0x40 0x2 Number of L1 D-cache ways.e
icache-size int 0x4000-0x100000 0x8000 L1 I-cache size, in bytes.
icache-ways int 0x1-0x40 0x2 Number of L1 I-cache ways.e
l2cache-size int 0x0-0x1000000 0x80000 L2 cache size, in bytes.
l2cache-ways int 0x1-0x40 0x10 Number of L2 cache ways.e
ARMAEMv8AMPCT - TLB parameters

This section describes the parameters.

Table 5-25 ARMAEMv8AMPCT Translation Lookaside Buffer (TLB) parameters

Parameter Type Allowed values Default value Description
stage12_tlb_size int 0x1-0xFFFFFFFF 0x80 Number of stage 1 and stage 2 TLB entries.
stage1_tlb_size int 0x0-0xFFFFFFFF 0x0 Number of stage 1 TLB entries.
stage2_tlb_size int 0x0-0xFFFFFFFF 0x0 Number of stage 2 TLB entries.
stage1_walkcache_size int 0x0-0xFFFFFFFF 0x0 Number of stage 1 TLB walk cache entries.
stage2_walkcache_size int 0x0-0xFFFFFFFF 0x0 Number of stage 2 TLB walk cache entries.
instruction_tlb_size int 0x0-0xFFFFFFFF 0x0 Number of stage 1 and stage 2 ITLB entries. 0x0 for unified ITLB + DTLB.
enable_tlb_contig_check bool true, false true Check consistency of TLB entries in regions with the Contiguous Bit set.
has_tlb_conflict_abort bool true, false false Inconsistent TLB content generates aborts.
use_tlb_contig_hint bool true, false false Pagetable entries with the Contiguous Bit set generate large TLB entries.
ARMAEMv8AMPCT - cryptography parameters

This section describes the parameters.

Table 5-26 ARMAEMv8AMPCT cryptography parameters

Parameter Type Allowed values Default value Description
cpu[n].crypto_aes int 0x0-0x2 0x2 AES hash level. 0 = AES-128, 1 = AES-192, 2 = AES-256.
cpu[n].crypto_sha1 int 0x0-0x1 0x1 Enable SHA1.
cpu[n].crypto_sha256 int 0x0-0x1 0x1 Enable SHA256.
ARMAEMv8AMPCT - GIC parameters

This section describes the parameters.

Table 5-27 ARMAEMv8AMPCT Generic Interrupt Controller (GIC) parameters

Parameter Type Allowed values Default value Description
dic-spi_count int 0x0-0xE0 0x40 Number of Shared Peripheral Interrupts (SPIs) supported.
GICDISABLE bool true, false true Disable the GICv3 interface in each core. Leave enabled unless the platform contains a GICv3 distributor.
gicv3.BPR-min int 0x0-0x3 0x2 Minimum value for GICC_BPR. Non-secure copy will be this value + 1.
gicv3.IIDR_base int

0x0-0xFFFFFFFF

0x43B Base value for calculating GICC_IIDR value.
gicv3.STATUSR-implemented bool true, false true If GICv3 core interface enabled, enable STATUS registers.
internal_vgic bool true, false true Enable VGIC peripheral. Enable unless a shared VGIC is present.
non_secure_vgic_alias_when_ns_only int

0x0-

0xFFFFFFFFFFFF

0x0 If no EL3 and no Secure state, the VGIC has a Secure alias. If this parameter is nonzero, the model forms a Non-secure alias from its value for the VGIC, aligned to 32KiB.
ARMAEMv8AMPCT - abort parameters

This section describes the parameters.

Table 5-28 ARMAEMv8AMPCT abort parameters

Parameter Type Allowed values Default value Description
abort_execution_from_device_memory bool true, false false Abort on execution from device memory.
ext_abort_normal_cacheable_read_is_sync bool true, false true Synchronous reporting of normal cacheable-read external aborts.
ext_abort_normal_noncacheable_read_is_sync bool true, false true Synchronous reporting of normal non-cacheable read external aborts.
ext_abort_device_read_is_sync bool true, false true Synchronous reporting of device read external aborts.
ext_abort_so_read_is_sync bool true, false true Synchronous reporting of strongly ordered read external aborts.
ext_abort_normal_cacheable_write_is_sync bool true, false false Synchronous reporting of normal cacheable write external aborts.
ext_abort_normal_noncacheable_write_is_sync bool true, false false Synchronous reporting of normal non-cacheable write external aborts.
ext_abort_device_write_is_sync bool true, false false Synchronous reporting of device write external aborts.
ext_abort_so_write_is_sync bool true, false true Synchronous reporting of strongly ordered write external aborts.
ext_abort_ttw_cacheable_read_is_sync bool true, false true Synchronous reporting of TTW cacheable read external aborts.
ext_abort_ttw_noncacheable_read_is_sync bool true, false true Synchronous reporting of TTW non-cacheable read external aborts.
ext_abort_prefetch_is_sync bool true, false true Synchronous reporting of instruction fetch external aborts.
ext_abort_fill_data int - 0xFDFDFDFCFCFDFDFD Returned data, if external aborts are asynchronous.
unpredictable_exclusive_abort_memtype int 0x0-0x2 0x0 MMU abort if exclusive access is not supported. 0 = none, exclusives allowed in all memory, 1 = exclusives abort in Device memory, 2 = exclusives abort in any memory type other than WB inner cacheable.
ARMAEMv8AMPCT - debug architecture parameters

This section describes the parameters.

Table 5-29 ARMAEMv8AMPCT debug architecture parameters

Parameter Type Allowed values Default value Description
DBGPIDR int

0x0-

0xFFFFFFFFFF

0x0 If zero, build a value for the DeBuG Peripheral Identification Register (DBGPIDR). If nonzero, override DBGPIDR with this value.
cpu[n].number-of-breakpoints int 0x2-0x10 0x10 Number of breakpoints.
cpu[n].number-of-watchpoints int 0x2-0x10 0x10 Number of watchpoints.
cpu[n].number-of-context-breakpoints int 0x0-0x10 0x10 Number of context-aware breakpoints.
cpu[n].unpredictable_WPMASKANDBAS int 0x0-0x3 0x1 Constrained unpredictable handling of watchpoints when mask and BAS fields specified. 0 = IGNOREMASK, 1 = IGNOREBAS, 2 = REPEATBAS8, 3 = REPEATBAS.
cpu[n].unpredictable_non-contigous_BAS bool true, false true Treat non-contiguous BAS field in watchpoint control register as all ones.
cpu[n].cti-number_of_triggers int 0x0-0x8 0x8 Number of CTI event triggers.
cpu[n].cti-intack_mask int 0x0-0xFF 0x1 Set bits mean the corresponding triggers need software acknowledgment through CTIINTACK. One bit per trigger.
watchpoint-log2secondary_restriction int 0x0-0x3F 0x0 Log2(secondary restriction of FAR/EDWAR) on watchpoint hit for load/store operations.
ARMAEMv8AMPCT - simulator parameters

This section describes the parameters.

Table 5-30 ARMAEMv8AMPCT simulator parameters

Parameter Type Default value Description
scheduler_mode int 0x0-0x2 Control instruction interleaving. 0x0 = default long quantum, 0x1 = low latency mode, short quantum and signal checking, 0x2 = lock-breaking mode, long quantum with additional context switches near load-exclusive instructions.
cpu[n].max_code_cache int - Maximum cache size for code translations, in bytes.
ARMAEMv8AMPCT - semihosting parameters

This section describes the parameters.

Semihosting is a method of running your target software on the model to communicate with the host environment. The AEMs permit the target C library to access the I/O facilities of the host computer, such as the filesystem, keyboard input, and clock.

The semihosting parameters are repeated in groups for each core in the cluster, from cpu0 onwards.

Table 5-31 ARMAEMv8AMPCT semihosting parameters

Parameter Type Allowed values Default value Description
cpu[n].semihosting-ARM_SVC int

0x0-0xFFFFFFFF

0x123456 A32 SVC number for semihosted calls.
cpu[n].semihosting-Thumb_SVC int

0x0-0xFFFFFFFF

0xAB T32 SVC number for semihosted calls.
cpu[n].semihosting-cmd_line string - - Program name and arguments, argc, argv, for target programs using the semihosted C library.
cpu[n].semihosting-cwd string - - Base directory for semihosting file access.
cpu[n].semihosting-enable bool true, false true Enable semihosting of SVC instructions.
cpu[n].semihosting-heap_base int - 0x00000000 Virtual address of heap base.
cpu[n].semihosting-heap_limit int - 0x0F000000 Virtual address of top of heap.
cpu[n].semihosting-stack_base int - 0x10000000 Virtual address of base of descending stack.
cpu[n].semihosting-stack_limit int - 0x0F000000 Virtual address of stack limit.

ARMAEMv8AMPCT - boundary features and architectural checkers

Boundary features and architectural checkers are model capabilities that help your development and testing process by exposing latent problems in the target code.

Certain boundary features or architectural checkers, however, might have an adverse effect on the overall running speed of target code.

ARMAEMv8AMPCT - IMPLEMENTATION DEFINED features

Some aspects of the behavior of the processor are implementation defined in the ARM architecture, meaning that they can legally vary between different implementations.

Take care with code that uses these facilities if you intend to run it across multiple ARM implementations, because they might or might not be present.

a

This behavior is model-specific, with no hardware equivalent.

b

unpredictable.

c 

Unified caches allocate lines only if these parameters are enabled at both I-side and D-side.

d

As read from DCZID_EL0.

e 

Sets are implicit from size.

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