3.3 Base - interrupt assignments

The platform assigns the Shared Peripheral Interrupts (SPIs) and Private Peripheral Interrupts (PPIs) on the GIC.

Note:

SPI and PPI numbers are mapped onto GIC interrupt IDs as the ARM Generic Interrupt Controller Specification describes.

Table 3-4 SPI GIC assignments

IRQ ID SPI offset Device
32 0 Watchdog, SP805
34 2 Dual-Timer 0, SP804
35 3 Dual-Timer 1, SP804
36 4 Real-time Clock, PL031
37 5 UART0, PL011
38 6 UART1, PL011
39 7 UART2, PL011
40 8 UART3, PL011
41 9 MCI, PL180, MCIINTR0
42 10 MCI, PL180, MCIINTR1
43 11 AACI, PL041
44 12 KMI - Keyboard, PL050
45 13 KMI - Mouse, PL050
46 14 Color LCD Controller, PL111
47 15 Ethernet, SMSC 91C111
56 24 Trusted Watchdog, SP085
57 25 AP_REFCLK, Generic Timer, CNTPSIRQ
58 26 AP_REFCLK, Generic Timer, CNTPSIRQ1
59 27 EL2 Generic Watchdog WS0
60 28 EL2 Generic Watchdog WS1
73 41 VFS2
74 42 Virtio block device
80 48 TZC-400 interrupt
92 60 cluster0.cpu0 PMUIRQ
93 61 cluster0.cpu1 PMUIRQ
94 62 cluster0.cpu2 PMUIRQ
95 63 cluster0.cpu3 PMUIRQ
96 64 cluster1.cpu0 PMUIRQ
97 65 cluster1.cpu1 PMUIRQ
98 66 cluster1.cpu2 PMUIRQ
99 67 cluster1.cpu3 PMUIRQ
117 85 HD LCD Controller, PL370
139 107 Trusted Random Number Generator

Table 3-5 PPI GIC assignments

IRQ ID PPI offset Device
22 6 DCC, comms channel, interrupt
23 7 PMU, performance counter, overflow
24 8 CTI, Cross Trigger Interface, interrupt
25 9 Virtual CPU interface maintenance interrupt
26 10 Hypervisor timer interrupt
27 11 Virtual timer interrupt
29 13 Secure physical timer interrupt
30 14 Non-secure physical timer interrupt
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