5.5.2 VE - differences in memory aliasing

The model implements address space aliasing of the DRAM. The same physical memory locations are visible at different addresses.

The lower 2GB of the DRAM are accessible at 0x00_80000000. The full 8GB of DRAM are accessible at 0x08_00000000 and again at 0x80_00000000.

You can configure memory aliasing with the daughterboard.dram_alias parameter.

Table 5-32 AEMv8-A simulator parameters

Parameter Type Default value Description
daughterboard.dram_alias bool true Alias the bottom 2GB region in upper memory.
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