3.2.2. Setting up with a different directory structure

The makefiles for both Verilog compilation and software compilation work with the directory structure that Figure 3.1 shows. If you require a different structure you must modify the supplied software compilation makefile and Verilog compilation makefile.

Software compilation makefile

Each software testcode requires its own specific makefile. The DesignStart FPGA testbench comes with one example testcode, located in /designstart_FPGA/resources/fpga_testbench/fpga/testcodes/designtest_m0/makefile.

To replace the <cortexm0_designstart> path with the appropriate value in the makefile, edit the following line:

#============================================================
# EDIT the following to point to the CMSIS directory location
# downloaded as part of the DesignStart core
#============================================================
CMSIS_CORE_DIR    = ../../../../../../<cortexm0_designstart>/software/cmsis
#============================================================

Verilog compilation makefile

The Verilog compilation makefile is located in /designstart_FPGA/resources/fpga_testbench/fpga/rtl_sim/tbench.vc

To replace the <cortexm0_designstart> path with the appropriate value, edit the following four lines:

// ============= Cortex M0 DesignStart search path =============
-y ../../../../../<cortexm0_designstart>/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog
-y ../../../../../<cortexm0_designstart>/cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog
-y ../../../../../<cortexm0_designstart>/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog
-y ../../../../../<cortexm0_designstart>/cores/cortexm0_designstart_r1p0/logical/models/cells
Copyright © 2015-2016 ARM. All rights reserved.ARM DUI 0934B
Non-ConfidentialID062017