3.3.3. Compiling the RTL

After you have configured the environment, you must compile the Verilog RTL in the rtl_sim directory. To do this, use the following command:

</designstart_FPGA/resources/fpga_testbench/fpga/rtl_sim> make compile

This starts the compilation process. The process uses a Verilog command file tbench.vc, which specifies the location of the all required verilog design files. It also specifies any simulation specific parameters and definitions. The compile stage ignores the TESTNAME setting.

You can use the command line to override variables in the makefile. For example, the following command line specifies that Modelsim is used for compilation:

<designstart_FPGA /resources/fpga_testbench/fpga/rtl_sim> make compile SIMULATOR=mti
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