2.2. Design files

The testbench files are located in /resources/fpga_testbench/fpga/verilog. See the directory structure in Figure 1.1 for more information.

Table 2.1 shows the Verilog files that are included in the verilog folder.

Table 2.1. Verilog files for FPGA testbench

File nameDescription
tb_fpga.vTop level testbench. Instantiates peripherals below and FPGA top level.
cmsdk_uart_capture.vGenerates messages to simulator console from UART RS232 output.
cyclone_crcblock.vDummy placeholder for inbuilt silicon on FPGA.
cyclone_prblock.vDummy placeholder for inbuilt silicon on FPGA.



Behavioral model of GSI SSRAM used on MPS2 board.
IS66WVE409616BLL.vBehavioral model of ISSI PSRAM used on MPS2 board.
scc_tb.vBehavioral model of SCC interface from Microcontroller to FPGA.

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