2.1. System hierarchy

Figure 2.1 shows the FPGA testbench hierarchy, containing the Cortex-M0 processor from DesignStart and a modified CMSDK system. This indicates where the source code from the RTL testbench goes.

Figure 2.1. FPGA test structure

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The FPGA includes extra peripherals and devices outside of the CMSDK system required to interface to the peripherals present on the MPS2 board. These peripherals include the:

The FPGA file structure and connectivity is different from the ARM Cortex-M0 DesignStart Design Kit because the FPGA supports partial reconfiguration. For the FPGA structure, the Cortex-M0 processor from DesignStart is delivered as an encrypted partial reconfiguration bit stream. To achieve this in the FPGA, the Cortex-M0 processor from DesignStart has been separated from the CMSDK system.

The differences in structure and connectivity are important when source code that might have been developed using the Cortex-M0 DesignStart Design Kit is applied to the FPGA for simulation and testing. Within the CMSDK system, it is seen that the AHB and APB bus structures, clocks and reset signals, are similar.

However, you should be aware that there is a change in connectivity between the Cortex-M0 processor from DesignStart and the CMSDK system, with the FPGA structure passing all the Cortex-M0 signals out of the CMSDK system. There are differences in the memory map too, with the FPGA having a number of extra peripherals present. You can see the differences by comparing the cmsdk_mcu_addr_decode.v files present in both CMSDK systems.This means if you develop new functionality using the Cortex-M0 DesignStart Design Kit, then this functionality should be ported to the FPGA DesignStart testbench and the simulation rerun to ensure the functionality is maintained. After that you can build the FPGA and prototype with the new functionality using the MPS2 board.

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