4.1. About the software tests

The Cortex-M0 DesignStart FPGA testbench is able to run two forms of software test, both those written for directly for the FPGA, and also those targeted at the Cortex-M0 DesignStart RTL testbench. This is because both FPGA and RTL structures use the CMSDK with standardized memory map.


The FPGA memory map is a superset of the CMSDK memory map and includes the peripherals fitted to the MPS2 board, outside of the core FPGA.

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