1.4.2. Processor support

The Cortex-M0 DesignStart FPGA Prototyping Kit supports the Cortex-M0 processor from DesignStart.

Table 1.2 shows the differences in the features available in the full Cortex-M0 processor and the Cortex-M0 processor from DesignStart.

Table 1.2. Cortex-M0 processor and Cortex-M0 processor from DesignStart feature differences

Feature Full Cortex-M0 processor Cortex-M0 processor from DesignStart
Verilog code Commented plain-text RTLFlattened and obfuscated RTL
AMBA®3 AHB-Lite interface Master and optional slave portsMaster port only
ARMv6-M instruction setARMv6-M instruction set supportARMv6-M instruction set support
Multiplier options Fast single-cycle or small 32-cycleFast single cycle multiplier
Nested vectored interrupt controller (NVIC) 1-32 interrupt inputs32 interrupt inputs only
Wake-up Interrupt Controller (WIC)OptionalNone
Architectural clock gating OptionalNone
24-bit system timer, SysTickOptional reference clockReference clock supported
Hardware debugger interface Optional Serial-Wire or JTAG Only available in the FPGA bitfile
Hardware debug support Optional single step with up to four breakpoints, up to two watchpoints and PC samplingOnly available in the FPGA bitfile
Low-power signaling and domains Optional state-retention power domains and power control signalingSLEEPING, TXEV and RXEV signaling only

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