SoC Designer CDP v4.1 HDL Cosimulation Guide

Version 9.1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the SoC Designer CoDesign Package
2 Installing and Configuring Cosimulation Software
2.1 CDP Licensing
2.2 CoDesign Package components
2.2.1 Transactors present in the CoDesign Package
2.2.2 Cosimulation kernel libraries
2.3 Minimum Requirements
2.3.1 Cosimulation with Mentor Graphics ModelSim
2.4 Preparing for Cosimulation
2.4.1 Adding transactors to your SoC Designer system
2.4.2 Configuring Cosimulation in SoC Designer
2.4.3 Generating the Proxy Module
2.4.4 Modifying the top-level HDL design
2.4.5 Modifying RTL memory HDL codes (Optional)
2.4.6 Invoking SoC Designer Simulator and a HDL simulator
2.4.7 Proceeding with Cosimulation
2.5 Preparing for Cosimulation with ModelSim and Verilog
2.6 Preparing for Cosimulation with NCSim and Verilog
2.7 Preparing for Cosimulation with VCS with Verilog
2.8 Starting SoC Designer Cosimulation
2.8.1 Starting from SoC Designer Canvas
2.8.2 Starting Cosimulation separately
2.8.3 Starting Cosimulation in batch mode
2.8.4 Starting Cosimulation in slaveable simulator mode
2.9 Restarting Cosimulation
2.9.1 ModelSim
2.9.2 NCSim
2.9.3 VCS
2.10 Interaction between SoC Designer Simulator and an HDL simulator
3 CDP HDL Cosimulation Reference
3.1 Configuring CDP
3.1.1 HDL Cosimulation setup
3.2 Generated files for Cosimulation
3.2.1 ModelSim and Verilog
3.2.2 NCSim and Verilog
3.2.3 VCS and Verilog
3.3 CDP synchronization model
3.4 Combinatorial signals
3.5 Modifying RTL memory codes for debug support
3.6 Configuring endianness
3.7 Controlling Cosimulation through environment variables
3.7.1 Running multiple sessions of Cosimulation on a single host using MXCOSIM_SOCKFILENAME_SUFFIX
3.7.2 Changing the behavior of NCSim and VCS Cosimulation using MXCOSIM_CONTROL
3.8 Creating a new transactor
3.8.1 Example Transaction / Signal transactor
3.9 Direct HDL signal linking
3.9.1 Signal master ports
3.9.2 Signal slave ports
A AMBA® 3 AXI4 Transactors
A.1 About the AXI4 transactors
A.1.1 AXI transactor functionality
A.2 Component port interfaces
A.3 Model parameters
A.4 Supported signal bit widths
A.4.1 Configuring bit width for address and data
A.5 RTL memory debug support
B AMBA® 3 AXIv2 Transactors
B.1 About the AXIv2 transactors
B.1.1 AXI transactor functionality
B.2 Component port interfaces
B.3 Model parameters
B.4 Supported signal bit widths
B.4.1 Configuring bit width for address and data
B.5 RTL memory debug support
C AMBA® 2 AHBv2 Transactors
C.1 About the AHBv2 transactors
C.1.1 Naming conventions for AHBv2 transactors
C.1.2 AHBv2 Transactor Functionality
C.2 AHBv2M_T2S transactor features
C.2.1 SoC Designer interfaces
C.2.2 Model parameters
C.2.3 Connecting transactor signals to an HDL module
C.2.4 AHB-Lite support
C.3 AHBv2M_S2T transactor features
C.3.1 SoC Designer interfaces
C.3.2 Model parameters
C.3.3 Connecting transactor signals to an HDL module
C.3.4 AHB-Lite support
C.4 AHBv2S_T2S transactor features
C.4.1 SoC Designer interfaces
C.4.2 Model parameters
C.4.3 Connecting transactor signals to an HDL module
C.4.4 AHB-Lite support
C.5 AHBv2S_S2T transactor features
C.5.1 SoC Designer interfaces
C.5.2 Model parameters
C.5.3 Connecting transactor signals to an HDL module
C.5.4 AHB-Lite support
C.6 Debugging features
C.6.1 RTL memory debug support
C.7 Supported signal bit widths
D AMBA® APB Transactors
D.1 About the APB transactors
D.1.1 APB transactor functionality
D.2 Component port interfaces
D.2.1 Differences in APB3 transactors
D.3 Model parameters
D.4 Debugging features
E Converting CDP 3.0 test bench files to CDP 4.0 test bench files
E.1 Upgrading to CDP 4.0
F Troubleshooting
F.1 Troubleshooting situations

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