Arm® Cortex®-M23 Devices Generic User Guide

Revision: r1p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-M23 processor and core peripherals
1.1.1. Cortex-M23 processor features summary
1.1.2. System-level interface
1.1.3. Security Extension
1.1.4. Cortex-M23 processor core peripherals
1.1.5. Armv8-M enablement
2. The Cortex-M23 Processor
2.1. Programmers model
2.1.1. Processor modes and privilege levels for software execution
2.1.2. Security states
2.1.3. Stacks
2.1.4. Core registers
2.1.5. Exceptions and interrupts
2.1.6. Data types
2.1.7. The Cortex Microcontroller Software Interface Standard
2.2. Memory model
2.2.1. Memory regions, types, and attributes
2.2.2. Device memory
2.2.3. Secure memory system and memory partitioning
2.2.4. Behavior of memory accesses
2.2.5. Software ordering of memory accesses
2.2.6. Memory endianness
2.2.7. Synchronization primitives
2.2.8. Programming hints for the synchronization primitives
2.3. Exception model
2.3.1. Exception states
2.3.2. Exception types
2.3.3. Exception handlers
2.3.4. Vector table
2.3.5. Exception priorities
2.3.6. Exception entry and return
2.4. Security state switches
2.5. Fault handling
2.5.1. Lockup
2.6. Power management
2.6.1. Entering sleep mode
2.6.2. Wakeup from sleep mode
2.6.3. Wakeup Interrupt Controller
2.6.4. External event input
2.6.5. Power management programming hints
3. The Cortex-M23 Instruction Set
3.1. Instruction set summary
3.2. CMSIS functions
3.3. CMSE
3.4. About the instruction descriptions
3.4.1. Operands
3.4.2. Restrictions when using PC or SP
3.4.3. Shift Operations
3.4.4. Address alignment
3.4.5. PC‑relative expressions
3.4.6. Conditional execution
3.5. Memory access instructions
3.5.1. ADR
3.5.2. CLREX
3.5.3. LDR and STR, immediate offset
3.5.4. LDR and STR, register offset
3.5.5. LDR, PC‑relative
3.5.6. LDM and STM
3.5.7. LDREX and STREX
3.5.8. LDA and STL
3.5.9. LDAEX and STLEX
3.5.10. PUSH and POP
3.6. General data processing instructions
3.6.1. ADC, ADD, RSB, SBC, and SUB
3.6.2. AND, ORR, EOR, and BIC
3.6.3. ASR, LSL, LSR, and ROR
3.6.4. CMP and CMN
3.6.5. MOV and MVN
3.6.6. MOVT
3.6.7. MULS
3.6.8. REV, REV16, and REVSH
3.6.9. SDIV and UDIV
3.6.10. SXT and UXT
3.6.11. TST
3.7. Branch and control instructions
3.7.1. B, BL, BX, and BLX
3.7.2. BXNS and BLXNS
3.7.3. CBZ and CBNZ
3.8. Miscellaneous instructions
3.8.1. BKPT
3.8.2. CPS
3.8.3. DMB
3.8.4. DSB
3.8.5. ISB
3.8.6. MRS
3.8.7. MSR
3.8.8. NOP
3.8.9. SEV
3.8.10. SG
3.8.11. SVC
3.8.12. TT, TTT, TTA, and TTAT
3.8.13. WFE
3.8.14. WFI
4. Cortex-M23 Peripherals
4.1. About the Cortex-M23 peripherals
4.2. Nested Vectored Interrupt Controller
4.2.1. Accessing the Cortex-M23 NVIC registers using CMSIS
4.2.2. Interrupt Set-enable Registers
4.2.3. Interrupt Clear-enable Registers
4.2.4. Interrupt Set-pending Registers
4.2.5. Interrupt Clear-pending Registers
4.2.6. Interrupt Active Bit Registers
4.2.7. Interrupt Target Non-secure Registers
4.2.8. Interrupt Priority Registers
4.2.9. Level-sensitive and pulse interrupts
4.2.10. NVIC usage hints and tips
4.3. System Control Space
4.3.1. The CMSIS mapping of the Cortex-M23 SCS registers
4.3.2. CPUID Register
4.3.3. Interrupt Control and State Register
4.3.4. Vector Table Offset Register
4.3.5. Application Interrupt and Reset Control Register
4.3.6. System Control Register
4.3.7. Configuration and Control Register
4.3.8. System Handler Priority Registers
4.3.9. System Handler Control and State Register
4.3.10. Auxiliary Control Register
4.3.11. SCS usage hints and tips
4.4. System timer, SysTick
4.4.1. SysTick Control and Status Register
4.4.2. SysTick Reload Value Register
4.4.3. SysTick Current Value Register
4.4.4. SysTick Calibration Value Register
4.4.5. SysTick usage hints and tips
4.5. Security Attribution and Memory Protection
4.5.1. Security Attribution Unit
4.5.2. Security Attribution Unit Control Register
4.5.3. Security Attribution Unit Type Register
4.5.4. Security Attribution Unit Region Number Register
4.5.5. Security Attribution Unit Region Base Address Register
4.5.6. Security Attribution Unit Region Limit Address Register
4.5.7. Memory Protection Unit
4.5.8. MPU Type Register
4.5.9. MPU Control Register
4.5.10. MPU Region Number Register
4.5.11. MPU Region Base Address Register
4.5.12. MPU Region Limit Address Register
4.5.13. MPU Memory Attribute Indirection Register 0 and MPU Memory Attribute Indirection Register 1
4.5.14. MPU mismatch
4.5.15. Updating an MPU region
4.5.16. MPU design hints and tips
4.6. I/O Port
A. Revisions

List of Tables

1. Typographical conventions
2.1. Summary of processor mode, execution privilege level, and stack use options
2.2. Core register set summary
2.3. Stack Pointer register
2.4. PSR register combinations
2.5. APSR bit assignments
2.6. IPSR bit assignments
2.7. EPSR bit assignments
2.8. PRIMASK register bit assignments
2.9. CONTROL register bit assignments
2.10. Memory access behavior
2.11. Memory region shareability and cache policies
2.12. CMSIS functions for exclusive access instructions
2.13. Properties of the different exception types
2.14. Extended priority
2.15. Exception return behavior
2.16. Security state transitions
3.1. Cortex-M23 instructions
3.2. CMSIS intrinsic functions to generate some Cortex-M23 instructions
3.3. CMSIS intrinsic functions to access the special registers
3.4. CMSIS intrinsic functions to access the Non-secure special registers
3.5. Condition code suffixes
3.6. Memory access instructions
3.7. Data processing instructions
3.8. ADC, ADD, RSB, SBC and SUB operand restrictions
3.9. Branch and control instructions
3.10. Branch ranges
3.11. Miscellaneous instructions
3.12. Security state and access permissions in the destination register
4.1. Core peripheral register regions
4.2. NVIC register summary
4.3. CMSIS access NVIC functions
4.4. NVIC_ISERn bit assignments
4.5. NVIC_ICERn bit assignments
4.6. NVIC_ISPRn bit assignments
4.7. NVIC_ICPRn bit assignments
4.8. NVIC_IABRn bit assignments
4.9. NVIC_ITNSn bit assignments
4.10. NVIC_IPRn bit assignments
4.11. Summary of the SCS registers
4.12. CPUID register bit assignments
4.13. ICSR bit assignments
4.14. VTOR bit assignments
4.15. AIRCR bit assignments
4.16. SCR bit assignments
4.17. CCR bit assignments
4.18. System fault handler priority fields
4.19. SHPR2 register bit assignments
4.20. SHPR3 register bit assignments
4.21. SHCSR bit assignments
4.22. ACTLR bit assignments
4.23. System timer registers summary
4.24. SYST_CSR bit assignments
4.25. SYST_RVR bit assignments
4.26. SYST_CVR bit assignments
4.27. SYST_CALIB register bit assignments
4.28. SAU registers
4.29. SAU_CTRL bit assignments
4.30. SAU_TYPE bit assignments
4.31. SAU_RNR bit assignments
4.32. SAU_RBAR bit assignments
4.33. SAU_RLAR bit assignments
4.34. Memory attributes summary
4.35. MPU registers summary
4.36. MPU_TYPE bit assignments
4.37. MPU_CTRL bit assignments
4.38. MPU_RNR bit assignments
4.39. MPU_RBAR bit assignments
4.40. MPU_RLAR bit assignments
4.41. MAIR_ATTR values for bits[3:2] when MAIR_ATTR[7:4] is 0000
4.42. MAIR_ATTR bit assignments when MAIR_ATTR[7:4] is not 0000
4.43. Memory region attributes for a microcontroller
A.1. Issue A

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Revision History
Revision A18 June 2018First release for r1p0
Copyright © 2018 Arm Limited or its affiliates. All rights reserved.DUI 1095A
Non-ConfidentialID062218