Section 2.7. Endianness

How does the MMCI handle endianness?

The MMCI supports only 3-bit accesses on its APB data buses. For a 32-bit system, the MMCI is bi-endian to the extent that it can support 32-bit accesses from a little-endian master and a big-endian master. In systems with wider data buses, data routing will have to be external to the MMCI. The registers in the MMCI do not manipulate sub-word data and or perform packing? Software would have to rearrange the data as necessary.

What about for registers containing data where a byte packing operation can be performed by some peripherals to have a 32-bit word register containing 4 bytes or 2 half-words? In this case, the ordering of the sub-word data inside the word must be arranged towards the endian mode. Does the MMCI perform any sub-word manipulation?

The registers in the MMCI do not manipulate sub-word data and or perform packing? Software would have to rearrange the data as necessary.

Does it mean that data manipulated by the MMCI to/from the card are only words. In this case, both HW and SW have nothing to care about?

Unfortunately, it is not as simple as that;

APB<->MMCI data transfer is word wide

MMCI<->card data transfer is byte wide (note that this is actually done via a serial line, but the MMC transfer length is in bytes)

So, if DATA [31:0] is written to the FIFO, the MMCI will send 4 bytes to the card. The byte order is DATA [7:0], DATA[15:8], DATA[23:16], DATA[31:24].

For Rx, if card sends 4 bytes, BYTE0, BYTE1, BYTE2 and BYTE3, the FIFO will contain one word:

DATA [31:24] = BYTE3

DATA [23:16] = BYTE2

DATA [15:8] = BYTE1

DATA [7:0] = BYTE0

What about command messages and related registers ie argument register and the four response registers?

The MMCI does not support sub-word data accesses. The MMCI always packs/unpacks the card data in the same way regardless of endianness.