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Applies to: C51 C Compiler


Information in this article applies to:


16-bit SFRs are composed of two consecutive addresses that contain the MSB and LSB (in either order) of the 16-bit register. Depending on the device, writing to the MSB or LSB "latches" the 16-bit value into the register. Subsequently, there are four possible configurations for a 16-bit SFR. They are:

The sfr16 keyword may be used to define some (but not all) 16-bit Special Function Registers. The two SFRs accessed by sfr16 must be organized so that the low byte is stored in memory first (or at the lower address). For example, if the LSB is at SFR address 0x9E and the MSB is at SFR address 0x9F, sfr16 may be used.

When you write to an sfr16, the code generated by the Keil C51 Compiler writes to the high byte first and then the low byte. In many cases, this is not the desired order.

If the order in which the bytes are written is important (this is the case with MANY 8051 devices) you must use the sfr keyword to define and access the SFRs. Then, you are assured of the order in which the SFRs are accessed.

The reason that sfr16 is implemented the way it is goes all the way back to the original Intel 8052. These devices offered only one 16-bit SFR, Timer 2. And, the 16-bit Timer 2 counter was implemented in the exact way that sfr16 works (except for the latching that happens after the last write). Over time more chip vendors created new 8051 devices and did not implement 16-bit SFRs in the same byte order as the original Intel 8052. Some 16-bit SFRs do not even have adjacent MSB and LSB registers. So, be careful when using sfr16.


Article last edited on: 2004-05-30 18:00:41

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