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Applies to: C51 C Compiler
Information in this article applies to:
I'm using the Keil PK51 Professional Developer's Kit with a Dallas DS80C390 Rev Bx Device in Contiguous Mode. I'm using the ROM(D512K) directive to generate compact code using the extended ACALL instructions. However, there is a potential chip problem with ACALL instructions in the DALLAS SEMICONDUCTOR ERRATA SHEET DS80C390 Revision B4 under item 6:
The ACALL instruction will not operate correctly in 24-bit contiguous mode if the memory location following the 3 byte instruction falls on a 64 kB page boundary (xx0000h).
Work around: None.
Be sure that ACALL instructions are not located close to a 64 kB page boundary (xx0000h).
What should I do?
The code generated by the Keil tools avoid this problem as follows:
Therefore, ACALL will not be the last instruction in a 64K Byte block and this chip problem cannot occur.
To be certain that no ACALL instructions are located at the end of a 64K Byte block by the assembler parts of your application code, you may reserve the last memory location in each code page using the LX51 Linker RESERVE directive. For example, in uVision under Options for Target - LX51 Locate - Reserve: enter:
C:0xFFFF-C:0xFFFF, C:0x1FFFF-C:0x1FFFF, C:0x2FFFF-C:0x2FFFF, C:0x3FFFF-C:0x3FFFF
This will ensure that there are no CPU instruction located at the last byte of a 64K Byte block in the memory segments 0, 1, 2, and 3.
Article last edited on: 2005-07-18 09:44:50
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