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DISABLE CACHE TO AVOID MEMORY READS

Applies to: MON51 Target Monitor

Answer


Information in this article applies to:


QUESTION

I am using Monitor-51 to debug a memory mapped FPGA design. When I modify a memory value in the memory window, it appears that not just the modify memory location is updated. Instead, all the values shown in the memory window seem to be read.

My problem is: the FPGA that is mapped into the 'external memory' has functionality (as is the case with SFR registers) and therefore, the additional write and read operations confuse the FPGA logic.

Is there a way to prevent additional read and write operations when using the uVision Debugger with a Target Monitor?

ANSWER

The Target Monitor tries to maximize the communication speed by combining memory access operations. Therefore, a Memory Cache is implemented. Instead of reading just a single byte, a larger memory block is read and copied into a local PC buffer. In this way, the uVision Debugger interacts much faster than without such a cache system.

You may avoid such additional memory reads from the target hardware when you:

MORE INFORMATION

Article last edited on: 2004-06-30 18:51:26

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