ARM Technical Support Knowledge Articles

INTERRUPT BEHAVIOUR ON INFINEON XC16X DEVICES

Applies to: C166 C Compiler

Answer


Information in this article applies to:


QUESTION

I have problems with disabling a timer interrupt on Infineon XC16x devices. The following sequence was successfully used on classic C16x devices, but appears to fail on the new Infineon XC16x:

__asm {
       ATOMIC  #4 ; Use ATOMIC sequence to avoid pipeline problems
       BCLR    GPT12E_T2IC_IE
       NOP
       NOP
       NOP                      ; Timer 2 Interrupt disabled
; at this point, I still get a Timer 2 interrupt

It appears that this sequence does not protect my code from Timer 2 interrupts. When I change the code to the following sequence, it seems to work as expected:

__asm {
       BCLR    PSW_IEN
       ATOMIC  #4
       BCLR    GPT12E_T2IC_IE
       NOP
       NOP
       ATOMIC  #4
       NOP
       NOP
       NOP
       ATOMIC  #2
       NOP
       BSET    PSW_IEN
}

It seems to be essential that PSW.IEN is cleared during this sequence. Is there a better solution? Does this also affect my Real-Time Operating Systems?

ANSWER

Your work-around sequence executes correctly on the XC16x. A read back of the IE (Interrupt Enable) flag is a better method and may be implemented in C with:

   IEN = 0;                /* Avoid pipeline effect for XC16x   */
   GPT12E_T2IC_IE  = 0;
   while (GPT12E_T2IC_IE); /* Wait till flag is really cleared. */
   IEN = 1;

This sequence ensures that the IE flag is clear when the interrupt system is re-enabled.

In contrast to classic C16x/ST10 devices, some of the old pipeline effects are solved in the new C166 V2 core (that is used by the XC161, XC164, and XC167 devices). Now, resetting PSW.IEN is immediately effective (no interrupt will happen afterwards). The old work-arounds (documented for C16x/ST10 core) are still OK on XC16x devices.

However, the Infineon C166 V2 core (which is used in the XC161, XC164, and XC167 devices) serves interrupts after ATOMIC when a single IE flag is disabled within the ATOMIC sequence. The interrupt module processes interrupts very early and delays execution just for the ATOMIC sequence.

Note: The assignment IEN=0 must not be part of an ATOMIC sequence. If it is, the interrupt request is delayed until the end of the ATOMIC sequence.

Important:

The change in the interrupt behaviour of XC16x may affect several Real Time Operating Systems.

MORE INFORMATION

SEE ALSO

Article last edited on: 2007-01-12 15:35:44

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential