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Applies to: C51 C Compiler
Information in this article applies to:
An interrupt may be taken after global interrupts are disabled (using EA=0) or after an individual interrupt is disabled (using IE.x = 0) if a single-cycle instruction immediately follows the instruction that clears the interrupt enable flag. This problem affects Silicon Labs C8051F12x and C8051F13x devices.
The optimized, pipelined architecture of these devices allows an interrupt to trigger before the state of the interrupt enable bit is finally cleared (and interrupts are disabled).
Repeat clearing the bit. For example:
EA=0; EA=0; /*** For SiLabs F12x/F13x ***/ /* protected code */ EA=1;
This is a confirmed issue with these devices. Refer to the Silicon Labs data sheet for these devices.
Article last edited on: 2007-04-26 11:15:43
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