|ARM Technical Support Knowledge Articles|
Applies to: ARM Development Tools
Information in this support solution applies to:
The Cortex-M3 CPU Core has a problem when executing LDRD with the base register in the list of the form LDRD Ra, Rb, [Ra, #imm]. The instruction may not complete after the load of the first destination register when an interrupt occurs during execution of the instruction.
Is this a serious problem that I need to be concerned with? Are the instructions actually generated by the RealView Compiler?
Yes, the instructions are generated by the RealView Compiler Version V184.108.40.2060 or before. RealView Compiler Versions 220.127.116.111 and later no longer generate this sequence. RealView Compiler update(V18.104.22.1682) is part of RealView MDK V3.30 and higher.
It actually depends on the device whether the instruction may cause problems or not. For most devices the instruction execution is correct when code is fetched from on-chip Flash ROM. Check with the silicon vendor for clarification of the errata.
For existing code you may check the image with the attached fromelf and scanning tool for the erroneous instruction. If the erroneous code is detected in the text file you will see the warning:
WARNING: Found 1 instances of LDRD code which are susceptible to the Cortex-M3 LDRD erratum (erratum #602117)
To automate the check, apply the following changes to your µVision project:
fromelf -c #L --output @L.txt
With these changes the check is performed every time you build your target application.
Request the files attached to this knowledgebase article.
Article last edited on: 2009-02-09 08:15:49
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