ARM Technical Support Knowledge Articles

How is the JTAG chain routed on the EB?

Applies to: EB (Emulation Baseboard)

Answer

The EB has two separate JTAG scan chains. A Debug chain and a Config chain:

Debug chain: Comprises the Core Tile (CT) ARM core and synthesized JTAG TAP controllers in the Logic Tile (LT). The Debug chain signals are prefixed with 'D_' on the EB schematic (*).

Config chain: Comprises the FPGA and PLDs on the EB. The Config chain signals are prefixed with 'C_' on the EB schematic (*).

(*)The EB Schematic is available from the Versatile Famiy CD (ARM\Versatile\EB_HBI0140\3.x\2\pcb\schematic\hpi0140c.pdf).

To provide extra flexibility the EB is fitted with 2 JTAG ports. J18 is called the JTAG ICE connector and J19 the ILA connector.

The JTAG ICE connector (J18) enables you to connect a JTAG run control unit such as Realview ICE (RVI). This allows you to debug software running on the ARM processor and also configure the EB FPGA using the progcards_rvi utility.

The ILA connector (J19) enables you to connect a Xilinx ChipScope compatible analyzer to the Config chain. This allows you to debug Logic Tiles designs. The ILA connector can be used in conjunction with the JTAG ICE connector, enabling you to configure/debug your FPGA whilst debugging code on the CPU.

The EB is fitted with a configuration switch (S1) which sets its mode of operation. The EB can either be in: Debug mode (S1 OFF) or Configuration mode (S1 ON). During normal hardware and software development, the EB operates in Debug mode. Configuration mode is used when programming the baseboard FPGA/PLDs.

Connectivity in different modes:

Debug mode (see Fig. 1 and Fig. 3):

• the ILA connector is enabled and accesses a subset of devices on the Config chain.
• the JTAG ICE connector is enabled and accesses all the devices on the Debug chain.


Configuration mode (see Fig. 2 and Fig. 4):

• the ILA connector is disabled.
• the JTAG ICE connector is enabled and accesses all the devices on the Config chain.

EB JTAG chain diagrams:

The set of diagrams below illustrate the JTAG chain routing. There are 2 diagrams representing each of the modes previously discussed (Debug and Configuration). The simplified diagram is there for clarity and the detailed diagram for completeness.


Simplified diagram of the Emulation Baseboard in Debug mode (Fig. 1).

(please select to magnify)



Detailed diagram of the Emulation Baseboard in Debug mode (Fig. 2).

(please select to magnify)



Simplified diagram of the Emulation Baseboard in Config mode (Fig. 3).

(please select to magnify)


Detailed diagram of the Emulation Baseboard in Config mode (Fig. 4).

(please select to magnify) 





Attachments: EB_JTAG_V7_DIAGRAM2.png , EB_JTAG_V7_DIAGRAM1.png , EB_JTAG_V7_DIAGRAM3.png , EB_JTAG_V7_DIAGRAM4.png

Article last edited on: 2009-04-14 13:34:23

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