|ARM Technical Support Knowledge Articles|
Applies to: ARM926EJ-S
I want to know how the ARM926EJ-S can perform transfers such that the data phase of the first transfer occurs in the same cycle as the address phase of the next transfer, by using SINGLE transfers
It is not possible, at least not in a predictable way, to get the ARM926EJ-S to perform back-to-back SINGLE transfers by using STRs alone. This is because, for every single STR transfer, there is an overhead of address calculation, mmu lookup, pagetable walks etc. all of which means that the core will probably issue an IDLE between each transfer. However, if you perform a Store Multiple (STM) of 2 or 3 words, or 6 or 7 words etc. you should get back-to-back SINGLE transfers. An STM of 2 or 3 words is a burst but, since the ARM926EJ-S cannot perform INCR (undefined length) bursts, it will perform them as SINGLES instead.
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