I have found some clock domain crossing paths in CoreSight ETM-R4. How do I constrain them?

Applies to: Debug and Trace

Answer

The ETM-R4 Configuration and Sign-off Guide explains how to constrain the clocks for synthesis. However, this explanation is only for synthesis considerations. On physical hardware ATCLK can be asynchronous to CLK. Hence, it can be run at a lower frequency.

In the guide, it recommends that all 3 clocks be defined to have synchronous relationships to each other and that false paths are not
used between clock domains. So, for example in system with a Cortex-R4 running at 400MHz, the typical constraints would be:

CLK 400MHz, ATCLK 400MHz and PCLKDBG 200MHz
 

Rate this article

Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Submit Rating and Feedback