ARM Technical Support Knowledge Articles

Do I need Level 1 memory if I have zero wait-state memory on the bus?

Applies to: ARM9 processors

Answer

Yes, it makes a significant difference to performance.

ARM9 processors generally achieve around 1.1 DMIPS/MHz when executing Dhrystone code entirely within their Level 1 memory system, which has a Harvard architecture.

However, even with zero wait-state memory, running from the bus incurs cycles of latency in the bus interface and contention between instruction and data accesses, either in the bus interface where the Level 2 interface is a single shared (Von Neumann) interface, or outside of the processor where the bus has a shared fabric or where the instruction and data accesses compete for access to the same memory slave.

For example, ARM968E-S will run Dhrystone approximately 80% faster from Level 1 Tightly Couple Memory (TCM) than from zero wait-state memory on the AHB bus running at processor speed.

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential