|ARM Technical Support Knowledge Articles|
Applies to: PL08x DMAC (DM & SM)
In the PL081 Technical Reference Manual, it says that the TransferSize value is decremented from its original value to zero. However, in the Technical Support Knowledge Article "PL08x DMAC (DM & SM) Section 2.5 TransferSize", its example shows that TransferSize increases from 0 to 3.
Which is correct?
Both the TRM and the Knowledge Article are correct. The TransferSize value is decremented down to zero, for both READs and WRITEs to/from the FIFO. However, in the case of reading the TransferSize value in the DMACCxControl register, the value returned will increase, indicating the number of <destination width> transfers *completed* on the bus. As it says in the Knowledge Article, "Then read TransferSize will increment from 0 to 12 (bytes) as the transfer progresses" meaning that if you were to read the DMACCxControl register TransferSize bits ([11:0]) you would see this value increase as indicated.
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