|ARM Technical Support Knowledge Articles|
Applies to: AMBA Design Kit (ADK)
The interrupts coming in to the interrupt controller are assumed to be asynchronous to the interrupt.v clock (HCLK); they are synchronised internally to the HCLK domain. The TRM states: "The IRQ and FIQ request logic has an asynchronous path. This enables interrupts to be asserted when the clock is disabled." This takes place in module ICSynctoHCLK; please see ICSynctoHCLK.v in the Interrupt/verilog/rtl_source directory under ADK for more details. Since the interrupts are level triggered, it is important that the incoming interrupt request remains active HIGH until it has been acknowledged by the core.
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