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Applies to: PL190 Vectored Interrupt Controller
PL190 contains synchronizers for its own internal use of asynchronous signals, but the paths through PL190 to the nVICIRQ and nVICFIQ outputs (which drive the processor's nIRQ & nFIQ inputs) are combinatorial.
This allows interrupts to wake the processor from sleep modes even if the PL190 clock (usually the AHB bus clock) is gated during sleep.
If the interrupt sources come from an asynchronous clock domain, and if the processor does not support asynchronous interrupt request signals (for example, does not contain synchronizers for nIRQ and nFIQ), then external synchronizers must be added to synchronize the interrupt request lines into the processor's clock domain.
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