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I don't understand the description of background region priority under PRIVDEFENA in the TRM

Applies to: Cortex-M3


Page 9-6 of the Cortex-M3 Technical Reference Manual ARM DDI 0337G states:

"The background region acts as if it was region number 1 before any settable regions."

This wording is confusing. It means to say that the background region always has lower priority than any settable region.

The Memory Protection Unit (MPU) defines priority to increase with increasing region number, starting from region zero. Therefore the background region can simply be considered to have priority equal to -1 which will always be less than any enabled MPU regions.

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