ARM Technical Support Knowledge Articles

Which AHB-Lite BURST and TRANSFER types are produced by Cortex-M3 and Cortex-M4?

Applies to: Cortex-M3, Cortex-M4


AHB-Lite supports transfer types of:

IDLE - no transfer requested
NONSEQ - unrelated to previous transfer address; single transfer or start of a new burst
SEQ - subsequent transfer in a burst, following on from the previous transfer
BUSY - no transfer in this cycle but the current burst is still in progress

AHB-Lite supports burst types of:

SINGLE - a single transfer unrelated to the previous or subsequent transfers
INCR - a burst of one or more transfers with addresses consecutive to the first transfer
INCRx, WRAPx - fixed length bursts where x may be 4, 8 or 16

Bus accesses can come from three places in the processor:
I-side (instruction side) of the core
D-side (data side) of the core
Debug access port (DAP)

The I-side of the core only sends 32-bit reads of type SINGLE NONSEQ

The D-side of the core only sends INCR of unspecified length. They can be 8, 16 or 32 bit reads or writes if the burst has a length of 1. If the burst has more than one beat (i.e. includes one or more SEQ after the initial NONSEQ), they can only be 32-bit reads or writes.

The DAP only issues SINGLEs but it can issue word or sub-word size transfes (8/16/32 bit).

I-Code bus interface only produces I-side transfers. (SINGLE/NONSEQ/32-bit)
D-Code bus interface produces D-side and DAP transfers. (SINGLE/NONSEQ, INCR/NONSEQ and INCR/SEQ/32-bit)
System bus interface produces I-side, D-side and DAP transfers. (SINGLE/NONSEQ, INCR/NONSEQ and INCR/SEQ/32-bit)

Cortex-M3 and Cortex-M4 never issue BUSY transfers.

Cortex-M3 and Cortex-M4 never issue fixed length bursts.

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