ARM Technical Support Knowledge Articles

What is the impact of a failed instruction in the Mali200 pipeline? How many cycles of latency does a failed instruction introduce?

Applies to: Mali-200


If an instruction fails, all the earlier units in the pipeline will be re-executed.

This means that a single thread will be delayed by 128 cycles (as there are 128 stages in the pipeline. But in real use case, only a single cycle of
usable execution slots is lost each time. With enough active threads (which is the case most of the time), the effect of a failed instruction is only one extra cycle of total execution time.

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